@@ -497,6 +497,11 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
tx->callback_param = &info->comp;
dmaengine_submit(tx);
+ init_completion(&info->comp);
+
+ /* setup and start DMA using dma_addr */
+ dma_async_issue_pending(info->dma);
+
/* configure and start prefetch transfer */
ret = omap_prefetch_enable(info->gpmc_cs,
PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
@@ -504,10 +509,6 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
/* PFPW engine is busy, use cpu copy method */
goto out_copy_unmap;
- init_completion(&info->comp);
- dma_async_issue_pending(info->dma);
-
- /* setup and start DMA using dma_addr */
wait_for_completion(&info->comp);
tim = 0;
limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
The prefetch engine sends a dma request once a FIFO threshold has been met. No other requests are received until the previous request is handled. Starting an edma transfer (dma_async_issue_pending) results in any previous event for the dma channel to be cleared. Therefore, starting the prefetch engine before initiating the dma transfer may result in the prefetch triggering a dma request but instead of it being handled it can end up being cleared. This will result in a hang since the code will continue to wait for the dma request to complete. By initiating the dma request before enabling the prefetch engine this race condition is avoided and no dma request are missed/cleared. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> --- drivers/mtd/nand/omap2.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)