From patchwork Mon Mar 6 15:23:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gerlach X-Patchwork-Id: 9606981 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3B05D604DD for ; Mon, 6 Mar 2017 15:26:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2AF5A28447 for ; Mon, 6 Mar 2017 15:26:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1F7332844C; Mon, 6 Mar 2017 15:26:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C42962844C for ; Mon, 6 Mar 2017 15:26:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754380AbdCFPZy (ORCPT ); Mon, 6 Mar 2017 10:25:54 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:13220 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754353AbdCFPZt (ORCPT ); Mon, 6 Mar 2017 10:25:49 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v26FO6Pi025365; Mon, 6 Mar 2017 09:24:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1488813846; bh=1r3ZV2E13EI3ydc1kTpemTjAmoIHoW5CYZmZcvK8Ue4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=W+O/5F8OMTRc8t56SVSQeGG7UzROSSusqqWDBqWSk6hH/oUHcbJcjvyLSRqQfJ8OC l8TaDtvqPgxBBLWHgCRPcT3vcgqHcNIRosIx7agE9OP2sXIyVzEmT+Wlbu7KvwJBcY FLh0/4/L/lbtsy0Uk5ljDdYpRlBR2tWA09o2zf1M= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v26FO0kL018679; Mon, 6 Mar 2017 09:24:00 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 6 Mar 2017 09:24:00 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v26FO0qf017643; Mon, 6 Mar 2017 09:24:00 -0600 Received: from localhost (uda0274052.am.dhcp.ti.com [128.247.83.19]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v26FO0306440; Mon, 6 Mar 2017 09:24:00 -0600 (CST) From: Dave Gerlach To: Tony Lindgren CC: , , , Viresh Kumar , , Rob Herring , Nishanth Menon , Dave Gerlach , Lukasz Majewski , Yegor Yefremov Subject: [PATCH 1/5] ARM: dts: am33xx: Add updated operating-points-v2 table for cpu Date: Mon, 6 Mar 2017 09:23:38 -0600 Message-ID: <1488813822-26042-2-git-send-email-d-gerlach@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1488813822-26042-1-git-send-email-d-gerlach@ti.com> References: <1488813822-26042-1-git-send-email-d-gerlach@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP After the ti-cpufreq driver has been added, we can now drop the operating-points table present in am33xx.dtsi for the cpu and add an operating-points-v2 table with all OPPs available for all silicon revisions. Also add necessary data for use by ti-cpufreq to selectively enable the appropriate OPPs at runtime as part of the operating-points table. Information from AM335x Data Manual, SPRS717i, Revised December 2015, Table 5-7. Signed-off-by: Dave Gerlach Reviewed-by: Lukasz Majewski --- arch/arm/boot/dts/am33xx.dtsi | 87 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 74 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 9e96d60976b7..9e242943dcec 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -46,19 +46,7 @@ device_type = "cpu"; reg = <0>; - /* - * To consider voltage drop between PMIC and SoC, - * tolerance value is reduced to 2% from 4% and - * voltage value is increased as a precaution. - */ - operating-points = < - /* kHz uV */ - 720000 1285000 - 600000 1225000 - 500000 1125000 - 275000 1125000 - >; - voltage-tolerance = <2>; /* 2 percentage */ + operating-points-v2 = <&cpu0_opp_table>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -67,6 +55,79 @@ }; }; + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_conf>; + + /* + * The three following nodes are marked with opp-suspend + * because the can not be enabled simultaneously on a + * single SoC. + */ + opp50@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0x06 0x0010>; + opp-suspend; + }; + + opp100@275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0x00FF>; + opp-suspend; + }; + + opp100@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0020>; + opp-suspend; + }; + + opp100@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp100@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0040>; + }; + + opp120@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp120@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x06 0x0080>; + }; + + oppturbo@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + oppturbo@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x06 0x0100>; + }; + + oppnitro@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0x04 0x0200>; + }; + }; + pmu { compatible = "arm,cortex-a8-pmu"; interrupts = <3>;