From patchwork Wed May 17 15:50:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 9731545 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 131BF60363 for ; Wed, 17 May 2017 15:52:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 056EC26E78 for ; Wed, 17 May 2017 15:52:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EE31028654; Wed, 17 May 2017 15:52:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UPPERCASE_50_75 autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A90C26E78 for ; Wed, 17 May 2017 15:52:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753842AbdEQPwE (ORCPT ); Wed, 17 May 2017 11:52:04 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:52083 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751398AbdEQPwD (ORCPT ); Wed, 17 May 2017 11:52:03 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4HFpQOH025293; Wed, 17 May 2017 10:51:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495036286; bh=aosu0fulxRUgL4fmZakThJ9+84+67aOVw7KldCZvsB8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HvKARmdkVAr993ZyjGRQPJ4rdjtYWViti65+VU2DvJT3tTYb29KB+J5GDLX8MsXsz 5JuC82VY+P6dOnbkh406Uu/2ak0nT2qF2E8IpPCD6/injrvTUM4Fuaz11vXfVQWt2m 7Gdcg6FWhkiok/B/W1RV08L9YwhbrMf2l9omeiXI= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4HFpQjf000450; Wed, 17 May 2017 10:51:26 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Wed, 17 May 2017 10:51:25 -0500 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4HFp8dR008940; Wed, 17 May 2017 10:51:21 -0500 From: Tero Kristo To: , , , CC: , Subject: [PATCHv3 3/4] dt-bindings: clk: add omap4 clkctrl definitions Date: Wed, 17 May 2017 18:50:08 +0300 Message-ID: <1495036209-11298-4-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495036209-11298-1-git-send-email-t-kristo@ti.com> References: <1495036209-11298-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Contains offsets for all omap4 clkctrl main and optional clocks. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren --- include/dt-bindings/clock/omap4.h | 146 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 include/dt-bindings/clock/omap4.h diff --git a/include/dt-bindings/clock/omap4.h b/include/dt-bindings/clock/omap4.h new file mode 100644 index 0000000..e86c758 --- /dev/null +++ b/include/dt-bindings/clock/omap4.h @@ -0,0 +1,146 @@ +/* + * Copyright 2017 Texas Instruments, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __DT_BINDINGS_CLK_OMAP4_H +#define __DT_BINDINGS_CLK_OMAP4_H + +#define OMAP4_CLKCTRL_OFFSET 0x20 +#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) + +/* mpuss clocks */ +#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* tesla clocks */ +#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* abe clocks */ +#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) +#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) +#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) +#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) +#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) +#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) +#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) +#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) +#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) + +/* l4_ao clocks */ +#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) + +/* l3_1 clocks */ +#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_2 clocks */ +#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) + +/* ducati clocks */ +#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_dma clocks */ +#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_emif clocks */ +#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) + +/* d2d clocks */ +#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l4_cfg clocks */ +#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) + +/* l3_instr clocks */ +#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) + +/* ivahd clocks */ +#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) + +/* iss clocks */ +#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) + +/* l3_dss clocks */ +#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_gfx clocks */ +#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +/* l3_init clocks */ +#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) +#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) +#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) +#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0) +#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) + +/* l4_per clocks */ +#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) +#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) +#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) +#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) +#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) +#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) +#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) +#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) +#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) +#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0) +#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8) +#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0) +#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8) +#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0) +#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) +#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0) +#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8) +#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100) +#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108) +#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120) +#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128) +#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138) +#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140) +#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148) +#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150) +#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) +#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) + +/* l4_wkup clocks */ +#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) +#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) +#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) +#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) +#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) + +/* emu_sys clocks */ +#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) + +#endif