From patchwork Thu Apr 12 03:53:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "J, KEERTHY" X-Patchwork-Id: 10337815 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 30869603B5 for ; Thu, 12 Apr 2018 03:56:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 22C6A2857E for ; Thu, 12 Apr 2018 03:56:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 14B4A285A4; Thu, 12 Apr 2018 03:56:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A6BC32857E for ; Thu, 12 Apr 2018 03:56:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753077AbeDLD4F (ORCPT ); Wed, 11 Apr 2018 23:56:05 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:65157 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753019AbeDLDzt (ORCPT ); Wed, 11 Apr 2018 23:55:49 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3C3tMfc012162; Wed, 11 Apr 2018 22:55:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1523505322; bh=IbHnx2wKTu0HKm1lE/977Mco2c3dtov/h8ZPhoi6gAQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GCa92jSh9F6y+2RG//aeKbodtkamIC90dMiNxCtQjgqifzVFhb+Azzb1If1pbzY4+ A1R/uneCgnU8NC0k3EfTAJJLi/LWHq+cNBm8qX+DyHot7Krq5sjZOW5F0kWNM/W8w1 euBnUz3s4bEh/12/4XsPDLf5DTkOVPZv+xnlUHYE= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3C3tMxp008597; Wed, 11 Apr 2018 22:55:22 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Wed, 11 Apr 2018 22:55:21 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Wed, 11 Apr 2018 22:55:21 -0500 Received: from ula0393675.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3C3sQpv010150; Wed, 11 Apr 2018 22:55:18 -0500 From: Keerthy To: , , CC: , , , , , , , , Subject: [PATCH 14/14] ARM: OMAP2+: prm44xx: Introduce context save/restore for am43 PRCM IO Date: Thu, 12 Apr 2018 09:23:59 +0530 Message-ID: <1523505239-16229-15-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1523505239-16229-1-git-send-email-j-keerthy@ti.com> References: <1523505239-16229-1-git-send-email-j-keerthy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dave Gerlach There are two registers on am43x needed for IO daisy chain wake to work properly, however currently after an RTC+DDR cycle they are lost. We must take care to save and restore these before and after entering RTC mode otherwise IO daisy chain wake will stop working from DeepSleep after resuming. Signed-off-by: Dave Gerlach Signed-off-by: Keerthy --- arch/arm/mach-omap2/prm.h | 2 ++ arch/arm/mach-omap2/prm44xx.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index f0fb508..32e275f 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -179,6 +179,8 @@ int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod, u32 omap_prm_vp_check_txdone(u8 vp_id); void omap_prm_vp_clear_txdone(u8 vp_id); +void am43xx_prm_save_context(void); +void am43xx_prm_restore_context(void); #endif diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 47b657c..0d1111e 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -57,6 +57,13 @@ .reconfigure_io_chain = &omap44xx_prm_reconfigure_io_chain, }; +struct omap_prm_irq_context { + unsigned long irq_enable; + unsigned long pm_ctrl; +}; + +static struct omap_prm_irq_context omap_prm_context; + /* * omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST * hardware register (which are specific to OMAP44xx SoCs) to reset @@ -739,6 +746,28 @@ struct pwrdm_ops omap4_pwrdm_operations = { static int omap44xx_prm_late_init(void); +void am43xx_prm_save_context(void) +{ + omap_prm_context.irq_enable = + omap4_prm_read_inst_reg(AM43XX_PRM_OCP_SOCKET_INST, + omap4_prcm_irq_setup.mask); + + omap_prm_context.pm_ctrl = + omap4_prm_read_inst_reg(AM43XX_PRM_DEVICE_INST, + omap4_prcm_irq_setup.pm_ctrl); +} + +void am43xx_prm_restore_context(void) +{ + omap4_prm_write_inst_reg(omap_prm_context.irq_enable, + OMAP4430_PRM_OCP_SOCKET_INST, + omap4_prcm_irq_setup.mask); + + omap4_prm_write_inst_reg(omap_prm_context.pm_ctrl, + AM43XX_PRM_DEVICE_INST, + omap4_prcm_irq_setup.pm_ctrl); +} + /* * XXX document */