diff mbox

[1/2] OMAP3 SDRC: Fix autorefresh counter for Qimonda SDRAM 66.6MHz rate

Message ID 20090514185445.2152.97428.stgit@localhost.localdomain (mailing list archive)
State Superseded, archived
Headers show

Commit Message

Paul Walmsley May 14, 2009, 6:55 p.m. UTC 
The autorefresh counter value for the 66.6MHz rate for the Qimonda SDRAM
part is wrong; fix it.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 .../mach-omap2/sdram-qimonda-hyb18m512160af-6.h    |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)



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diff mbox

Patch

diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
index 74a92c8..304336b 100644
--- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
+++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
@@ -1,8 +1,8 @@ 
 /*
  * SDRC register values for the Qimonda HYB18M512160AF-6
  *
- * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2008-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2009 Nokia Corporation
  *
  * Paul Walmsley
  *
@@ -44,7 +44,7 @@  static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
 		.rate	     = 66666666,
 		.actim_ctrla = 0x290d2243,
 		.actim_ctrlb = 0x00012208,
-		.rfr_ctrl    = 0x0001d601,
+		.rfr_ctrl    = 0x0001d501,
 		.mr	     = 0x00000022,
 	},
 	[4] = {