From patchwork Thu Feb 11 18:17:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 78767 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o1BIKvNn017749 for ; Thu, 11 Feb 2010 18:21:18 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756808Ab0BKSU7 (ORCPT ); Thu, 11 Feb 2010 13:20:59 -0500 Received: from utopia.booyaka.com ([72.9.107.138]:35527 "EHLO utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756774Ab0BKSUy (ORCPT ); Thu, 11 Feb 2010 13:20:54 -0500 Received: (qmail 21100 invoked by uid 1019); 11 Feb 2010 18:20:53 -0000 MBOX-Line: From nobody Thu Feb 11 11:17:03 2010 Subject: [PATCH 06/13] OMAP clock: compress clock flags down to a u8 To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org From: Paul Walmsley Date: Thu, 11 Feb 2010 11:17:03 -0700 Message-ID: <20100211181701.795.87996.stgit@localhost.localdomain> In-Reply-To: <20100211181236.795.56094.stgit@localhost.localdomain> References: <20100211181236.795.56094.stgit@localhost.localdomain> User-Agent: StGit/0.15-22-gda30 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 11 Feb 2010 18:21:18 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 5dac307..7dc1ae7 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -126,7 +126,6 @@ struct clk { struct list_head children; struct list_head sibling; /* node for children */ unsigned long rate; - __u32 flags; void __iomem *enable_reg; unsigned long (*recalc)(struct clk *); int (*set_rate)(struct clk *, unsigned long); @@ -135,6 +134,7 @@ struct clk { __u8 enable_bit; __s8 usecount; u8 fixed_div; + u8 flags; #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ defined(CONFIG_ARCH_OMAP4) void __iomem *clksel_reg; @@ -189,20 +189,14 @@ extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); extern const struct clkops clkops_null; /* Clock flags */ -/* bit 0 is free */ -#define RATE_FIXED (1 << 1) /* Fixed clock rate */ -/* bits 2-4 are free */ -#define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ -/* bit 6 is free */ -#define CLOCK_IDLE_CONTROL (1 << 7) -#define CLOCK_NO_IDLE_PARENT (1 << 8) -#define DELAYED_APP (1 << 9) /* Delay application of clock */ -/* bit 10 is currently free */ -#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ -#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ -/* bit 13 is currently free */ -#define ALWAYS_ENABLED (1 << 14) -/* bits 15-31 are currently free */ +#define RATE_FIXED (1 << 0) /* Fixed clock rate */ +#define ENABLE_REG_32BIT (1 << 1) /* Use 32-bit access */ +#define CLOCK_IDLE_CONTROL (1 << 2) +#define CLOCK_NO_IDLE_PARENT (1 << 3) +#define DELAYED_APP (1 << 4) /* Delay application of clock */ +#define ENABLE_ON_INIT (1 << 5) /* Enable upon framework init */ +#define INVERT_ENABLE (1 << 6) /* 0 enables, 1 disables */ +#define ALWAYS_ENABLED (1 << 7) /* Clksel_rate flags */ #define DEFAULT_RATE (1 << 0)