From patchwork Wed Dec 8 06:18:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 389862 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB86K08S012981 for ; Wed, 8 Dec 2010 06:20:00 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753153Ab0LHGT7 (ORCPT ); Wed, 8 Dec 2010 01:19:59 -0500 Received: from utopia.booyaka.com ([72.9.107.138]:37191 "EHLO utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753218Ab0LHGTz (ORCPT ); Wed, 8 Dec 2010 01:19:55 -0500 Received: (qmail 23634 invoked by uid 1019); 8 Dec 2010 06:19:54 -0000 MBOX-Line: From nobody Tue Dec 7 23:18:40 2010 Subject: [PATCH 06/11] OMAP4: CM instances: add clockdomain register offsets To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org From: Paul Walmsley Cc: =?utf-8?q?Beno=C3=AEt?= Cousson Date: Tue, 07 Dec 2010 23:18:40 -0700 Message-ID: <20101208061839.30541.19958.stgit@twilight.localdomain> In-Reply-To: <20101208061657.30541.79824.stgit@twilight.localdomain> References: <20101208061657.30541.79824.stgit@twilight.localdomain> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Wed, 08 Dec 2010 06:20:01 +0000 (UTC) diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h index 63ef9e3..e2d7a56 100644 --- a/arch/arm/mach-omap2/cm1_44xx.h +++ b/arch/arm/mach-omap2/cm1_44xx.h @@ -40,6 +40,11 @@ #define OMAP4430_CM1_RESTORE_INST 0x0e00 #define OMAP4430_CM1_INSTR_INST 0x0f00 +/* CM1 clockdomain register offsets (from instance start) */ +#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 +#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 +#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 + /* CM1 */ /* CM1.OCP_SOCKET_CM1 register offsets */ diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h index 0fd0210..aa47450 100644 --- a/arch/arm/mach-omap2/cm2_44xx.h +++ b/arch/arm/mach-omap2/cm2_44xx.h @@ -46,6 +46,25 @@ #define OMAP4430_CM2_RESTORE_INST 0x1e00 #define OMAP4430_CM2_INSTR_INST 0x1f00 +/* CM2 clockdomain register offsets (from instance start) */ +#define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000 +#define OMAP4430_CM2_CORE_L3_1_CDOFFS 0x0000 +#define OMAP4430_CM2_CORE_L3_2_CDOFFS 0x0100 +#define OMAP4430_CM2_CORE_DUCATI_CDOFFS 0x0200 +#define OMAP4430_CM2_CORE_SDMA_CDOFFS 0x0300 +#define OMAP4430_CM2_CORE_MEMIF_CDOFFS 0x0400 +#define OMAP4430_CM2_CORE_D2D_CDOFFS 0x0500 +#define OMAP4430_CM2_CORE_L4CFG_CDOFFS 0x0600 +#define OMAP4430_CM2_CORE_L3INSTR_CDOFFS 0x0700 +#define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS 0x0000 +#define OMAP4430_CM2_CAM_CAM_CDOFFS 0x0000 +#define OMAP4430_CM2_DSS_DSS_CDOFFS 0x0000 +#define OMAP4430_CM2_GFX_GFX_CDOFFS 0x0000 +#define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS 0x0000 +#define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000 +#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 +#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 + /* CM2 */ diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h index e5190e9..729a644 100644 --- a/arch/arm/mach-omap2/prcm_mpu44xx.h +++ b/arch/arm/mach-omap2/prcm_mpu44xx.h @@ -37,6 +37,11 @@ #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400 #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 +/* PRCM_MPU clockdomain register offsets (from instance start) */ +#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0000 +#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0000 + + /* * PRCM_MPU * diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 95542ae..67a0d3f 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -56,6 +56,21 @@ #define OMAP4430_PRM_DEVICE_INST 0x1b00 #define OMAP4430_PRM_INSTR_INST 0x1f00 +/* PRM clockdomain register offsets (from instance start) */ +#define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000 +#define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000 +#define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000 +#define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000 +#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000 +#define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000 +#define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000 +#define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000 +#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000 +#define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000 +#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000 +#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 +#define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000 +#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 /* OMAP4 specific register offsets */ #define OMAP4_RM_RSTCTRL 0x0000