From patchwork Wed Sep 18 19:43:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 2909071 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6B4BA9F1E1 for ; Wed, 18 Sep 2013 19:44:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 248EA203DF for ; Wed, 18 Sep 2013 19:44:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3CFDC203DB for ; Wed, 18 Sep 2013 19:44:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751675Ab3IRToD (ORCPT ); Wed, 18 Sep 2013 15:44:03 -0400 Received: from mail-ee0-f49.google.com ([74.125.83.49]:43300 "EHLO mail-ee0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751494Ab3IRToB (ORCPT ); Wed, 18 Sep 2013 15:44:01 -0400 Received: by mail-ee0-f49.google.com with SMTP id d41so3697583eek.36 for ; Wed, 18 Sep 2013 12:44:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding:message-id; bh=oe9DC0JwFAl3b2uTE1hGiJjXKpsv6yBLtdWG5voa3PU=; b=Mq6IFFppz2CnUwoeax5vN0nLTAVOeEuXngYJDf+nB8ZQW0pY3eYY5WSeX9CgWE8vKr vdXRVBwW0ca629FH/oHMqU//avm2VrK2BHIfBXcobr9/Tz9cumg6cJDIAFn+sWa6ltAZ oDghZX2biK3jX4T/XHuEhjtiiD9dJy8WPTnB6NO0/Gb+NK0M1DF+Gtj4roYenwWfE2Nh 9jCK0LxTb6DHj3hyBTPiS9t3H9A7Or2gx+Y3XI9bqsFYyb5shVlKdas7MElU46yfcgU2 v5DNx5/NNNdkHX/N95nq2JaRUxv9QcKisPrxLSao1J5c5k9bDSKWV1U7tkXCVHbCJNXy /Vzw== X-Received: by 10.14.213.68 with SMTP id z44mr4849145eeo.70.1379533440091; Wed, 18 Sep 2013 12:44:00 -0700 (PDT) Received: from pali-elitebook.localnet ([2001:718:1e03:a01::1ca]) by mx.google.com with ESMTPSA id p5sm5557708eeg.5.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 18 Sep 2013 12:43:58 -0700 (PDT) From: Pali =?utf-8?q?Roh=C3=A1r?= To: Tony Lindgren Subject: [PATCH v4 2/2] RX-51: ARM errata 430973 workaround Date: Wed, 18 Sep 2013 21:43:56 +0200 User-Agent: KMail/1.13.7 (Linux/3.11.0-1+synaptics-generic; KDE/4.11.1; x86_64; ; ) Cc: linux-kernel@vger.kernel.org, Aaro Koskinen , linux-omap@vger.kernel.org, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, Nishanth Menon , Pavel Machek , Peter De Schrijver , Santosh Shilimkar , Ivaylo Dimitrov References: <1362044548-5398-1-git-send-email-pali.rohar@gmail.com> <201309182122.01570@pali> <20130918192731.GE9994@atomide.com> In-Reply-To: <20130918192731.GE9994@atomide.com> MIME-Version: 1.0 Message-Id: <201309182143.56555@pali> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-3.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, T_TVD_MIME_EPI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Closed and signed Nokia X-Loader bootloader stored in RX-51 nand does not set IBE bit in ACTLR and starting kernel in non-secure mode. So direct write to ACTLR by our kernel does not working and the code for ARM errata 430973 in commit 7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47 that sets IBE bit is a noop. In order to have workaround for ARM errata 430973 from non-secure world on RX-51 we needs Secure Monitor Call to set IBE BIT in ACTLR. This patch adds RX-51 specific secure support code and sets IBE bit in ACTLR during board init code for ARM errata 430973 workaround. Note that new function rx51_secure_dispatcher() differs from existing omap_secure_dispatcher(). It calling omap_smc3() and param[0] is nargs+1. ARM errata 430973 workaround is needed for thumb-2 ISA compiled userspace binaries. Without this workaround thumb-2 binaries crashing. So with this patch it is possible to recompile and run applications/binaries with thumb-2 ISA on RX-51. Signed-off-by: Ivaylo Dimitrov Signed-off-by: Pali Rohár --- I added note about difference between rx51_secure_dispatcher and omap_secure_dispatcher to commit message and also to code. arch/arm/mach-omap2/board-rx51.c | 12 +++++++ arch/arm/mach-omap2/omap-secure.c | 65 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/omap-secure.h | 11 +++++++ 3 files changed, 88 insertions(+) diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 773510556..db168c9 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -2,6 +2,8 @@ * Board support file for Nokia N900 (aka RX-51). * * Copyright (C) 2007, 2008 Nokia + * Copyright (C) 2012 Ivaylo Dimitrov + * Copyright (C) 2013 Pali Rohár * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -31,7 +33,9 @@ #include "mux.h" #include "gpmc.h" #include "pm.h" +#include "soc.h" #include "sdram-nokia.h" +#include "omap-secure.h" #define RX51_GPIO_SLEEP_IND 162 @@ -103,6 +107,14 @@ static void __init rx51_init(void) usb_musb_init(&musb_board_data); rx51_peripherals_init(); + if (omap_type() == OMAP2_DEVICE_TYPE_SEC) { +#ifdef CONFIG_ARM_ERRATA_430973 + pr_info("RX-51: Enabling ARM errata 430973 workaround\n"); + /* set IBE to 1 */ + rx51_secure_update_aux_cr(BIT(6), 0); +#endif + } + /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index b970440..146a7c4 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -3,6 +3,8 @@ * * Copyright (C) 2011 Texas Instruments, Inc. * Santosh Shilimkar + * Copyright (C) 2012 Ivaylo Dimitrov + * Copyright (C) 2013 Pali Rohár * * * This program is free software,you can redistribute it and/or modify @@ -70,3 +72,66 @@ phys_addr_t omap_secure_ram_mempool_base(void) { return omap_secure_memblock_base; } + +/** + * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls + * @idx: The PPA API index + * @process: Process ID + * @flag: The flag indicating criticality of operation + * @nargs: Number of valid arguments out of four. + * @arg1, arg2, arg3 args4: Parameters passed to secure API + * + * Return the non-zero error value on failure. + * + * NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because + * it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1 + */ +u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, + u32 arg1, u32 arg2, u32 arg3, u32 arg4) +{ + u32 ret; + u32 param[5]; + + param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */ + param[1] = arg1; + param[2] = arg2; + param[3] = arg3; + param[4] = arg4; + + /* + * Secure API needs physical address + * pointer for the parameters + */ + local_irq_disable(); + local_fiq_disable(); + flush_cache_all(); + outer_clean_range(__pa(param), __pa(param + 5)); + ret = omap_smc3(idx, process, flag, __pa(param)); + flush_cache_all(); + local_fiq_enable(); + local_irq_enable(); + + return ret; +} + +/** + * rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register + * @set_bits: bits to set in ACR + * @clr_bits: bits to clear in ACR + * + * Return the non-zero error value on failure. +*/ +u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits) +{ + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + + return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR, + 0, + FLAG_START_CRITICAL, + 1, acr, 0, 0, 0); +} diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index c4586f4..51b59c6 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -3,6 +3,8 @@ * * Copyright (C) 2011 Texas Instruments, Inc. * Santosh Shilimkar + * Copyright (C) 2012 Ivaylo Dimitrov + * Copyright (C) 2013 Pali Rohár * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -46,6 +48,11 @@ #define OMAP4_PPA_L2_POR_INDEX 0x23 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 +/* Secure RX-51 PPA (Primary Protected Application) APIs */ +#define RX51_PPA_HWRNG 29 +#define RX51_PPA_L2_INVAL 40 +#define RX51_PPA_WRITE_ACR 42 + #ifndef __ASSEMBLER__ extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, @@ -55,6 +62,10 @@ extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs); extern phys_addr_t omap_secure_ram_mempool_base(void); extern int omap_secure_ram_reserve_memblock(void); +extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, + u32 arg1, u32 arg2, u32 arg3, u32 arg4); +extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); + #ifdef CONFIG_OMAP4_ERRATA_I688 extern int omap_barrier_reserve_memblock(void); #else