--- drivers/clk/ti/dpll.c.orig	2016-03-21 22:53:16.379746383 +0100
+++ drivers/clk/ti/dpll.c	2016-03-22 01:48:36.988896607 +0100
@@ -114,6 +114,18 @@
 	.round_rate	= &omap2_dpll_round_rate,
 };
 
+static const struct clk_ops omap3630_dpll_ck_ops = {
+	.enable		= &omap3_noncore_dpll_enable,
+	.disable	= &omap3_noncore_dpll_disable,
+	.get_parent	= &omap2_init_dpll_parent,
+	.recalc_rate	= &omap3_dpll_recalc,
+	.set_rate	= &omap3_noncore_dpll_set_rate,
+	.set_parent	= &omap3_noncore_dpll_set_parent,
+	.set_rate_and_parent	= &omap3_noncore_dpll_set_rate_and_parent,
+	.determine_rate	= &omap3630_noncore_dpll_determine_rate,
+	.round_rate	= &omap3630_dpll_round_rate,
+};
+
 static const struct clk_ops omap3_dpll_per_ck_ops = {
 	.enable		= &omap3_noncore_dpll_enable,
 	.disable	= &omap3_noncore_dpll_disable,
@@ -448,6 +460,7 @@
 #ifdef CONFIG_ARCH_OMAP3
 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
 {
+	const struct clk_ops *ops = &omap3_dpll_ck_ops;
 	const struct dpll_data dd = {
 		.idlest_mask = 0x1,
 		.enable_mask = 0x7,
@@ -461,7 +474,10 @@
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};
 
-	of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
+	if (/* soc_is_omap3630() && */ strcmp(node->name, "dpll5_ck") == 0)
+		ops = &omap3630_dpll_ck_ops;
+
+	of_ti_dpll_setup(node, ops, &dd);
 }
 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
 	       of_ti_omap3_dpll_setup);
--- drivers/clk/ti/clock.h.orig	2016-03-21 22:55:09.011746383 +0100
+++ drivers/clk/ti/clock.h	2016-03-22 01:42:45.840896607 +0100
@@ -252,8 +252,12 @@
 					   u8 index);
 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
 				      struct clk_rate_request *req);
+int omap3630_noncore_dpll_determine_rate(struct clk_hw *hw,
+					 struct clk_rate_request *req);
 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 			   unsigned long *parent_rate);
+long omap3630_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+			      unsigned long *parent_rate);
 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 				    unsigned long parent_rate);
 
--- drivers/clk/ti/clkt_dpll.c.orig	2016-03-22 01:59:21.724896607 +0100
+++ drivers/clk/ti/clkt_dpll.c	2016-03-22 01:53:41.072896607 +0100
@@ -368,3 +368,46 @@
 
 	return dd->last_rounded_rate;
 }
+
+/**
+ * omap3630_dpll_round_rate - round a target rate for an OMAP DPLL
+ * @clk: struct clk * for a DPLL
+ * @target_rate: desired DPLL clock rate
+ *
+ * DM3730 errata (sprz319e), advisory 2.1, table 36 implementation
+ */
+long omap3630_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
+			      unsigned long *parent_rate)
+{
+	unsigned long rate;
+	struct dpll_data *dd;
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+
+	if (!clk || !clk->dpll_data)
+		return ~0;
+
+	dd = clk->dpll_data;
+	rate = target_rate == 120000000 ? *parent_rate : 0;
+
+	switch (rate) {
+	case 13000000:
+		dd->last_rounded_m = 443;
+		dd->last_rounded_n = 5;
+		break;
+	case 26000000:
+		dd->last_rounded_m = 443;
+		dd->last_rounded_n = 11;
+		break;
+	default:
+		return omap2_dpll_round_rate(hw, target_rate, parent_rate);
+	}
+	/* actual divide value, value of the register is n - 1 */
+	dd->last_rounded_n++;
+	dd->last_rounded_rate = rate * dd->last_rounded_m / dd->last_rounded_n;
+
+	pr_debug("clock: %s: fixed m = %d, n = %d, new_rate = %lu\n",
+		 clk_hw_get_name(hw), dd->last_rounded_m, dd->last_rounded_n,
+		 dd->last_rounded_rate);
+
+	return dd->last_rounded_rate;
+}
--- drivers/clk/ti/dpll3xxx.c.orig	2016-03-21 22:55:29.515746383 +0100
+++ drivers/clk/ti/dpll3xxx.c	2016-03-22 01:43:54.004896607 +0100
@@ -534,6 +534,33 @@
 	return 0;
 }
 
+int omap3630_noncore_dpll_determine_rate(struct clk_hw *hw,
+					 struct clk_rate_request *req)
+{
+	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+	struct dpll_data *dd;
+
+	if (!req->rate)
+		return -EINVAL;
+
+	dd = clk->dpll_data;
+	if (!dd)
+		return -EINVAL;
+
+	if (clk_get_rate(dd->clk_bypass) == req->rate &&
+	    (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
+		req->best_parent_hw = __clk_get_hw(dd->clk_bypass);
+	} else {
+		req->rate = omap3630_dpll_round_rate(hw, req->rate,
+					  &req->best_parent_rate);
+		req->best_parent_hw = __clk_get_hw(dd->clk_ref);
+	}
+
+	req->best_parent_rate = req->rate;
+
+	return 0;
+}
+
 /**
  * omap3_noncore_dpll_set_parent - set parent for a DPLL clock
  * @hw: pointer to the clock to set parent for
