From patchwork Tue Aug 30 14:58:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 9305495 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D4769607D2 for ; Tue, 30 Aug 2016 14:58:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C59C228C10 for ; Tue, 30 Aug 2016 14:58:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BA3D728C11; Tue, 30 Aug 2016 14:58:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1E30F28C14 for ; Tue, 30 Aug 2016 14:58:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755103AbcH3O6q (ORCPT ); Tue, 30 Aug 2016 10:58:46 -0400 Received: from arroyo.ext.ti.com ([198.47.19.12]:43450 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755019AbcH3O6m (ORCPT ); Tue, 30 Aug 2016 10:58:42 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u7UEw482024372; Tue, 30 Aug 2016 09:58:04 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u7UEw34N032327; Tue, 30 Aug 2016 09:58:03 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Tue, 30 Aug 2016 09:58:03 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u7UEw2tv004399; Tue, 30 Aug 2016 09:58:03 -0500 From: Grygorii Strashko To: Tony Lindgren CC: Sekhar Nori , , , , "J.D. Schroeder" , Tero Kristo , Lokesh Vutla , Grygorii Strashko Subject: [RESEND PATCH 1/2] ARM: dts: dra7: Fix clock data for gmac_gmii_ref_clk_div Date: Tue, 30 Aug 2016 17:58:00 +0300 Message-ID: <20160830145801.10364-1-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.9.2 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "J.D. Schroeder" This commit fixes the clock data inside the DRA7xx clocks device tree structure for the gmac_gmii_ref_clk_div clock. This clock is actually the GMAC_MAIN_CLK and has nothing to do with the register at address 0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is set to 1 in order to use the GMAC_RMII_CLK instead of the GMAC_RMII_HS_CLK, the kernel generates a clock divider warning: WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0() gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to have the parent of dpll_gmac_m2_ck always divided by 2 the warning is resolved and the clock tree is fixed up. Additionally, a new clock called rmii_50mhz_clk_mux is defined that does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the source clock for the RMII_50MHZ_CLK. Cc: Tero Kristo Cc: Lokesh Vutla Signed-off-by: J.D. Schroeder Reviewed-by: Trenton Andres Signed-off-by: Grygorii Strashko Acked-by: Tero Kristo --- Hi Tony, Originally this patch was posted (and acked) here https://lkml.org/lkml/2016/4/27/272, but it, unfortunatelly, has never been merged. So re-send + minor subj change. arch/arm/boot/dts/dra7xx-clocks.dtsi | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 8378b44..3f0c61d 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1718,13 +1718,20 @@ reg = <0x0c00>; }; - gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@13d0 { + rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 { #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_m2_ck>; + compatible = "ti,mux-clock"; + clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>; ti,bit-shift = <24>; reg = <0x13d0>; - ti,dividers = <2>; + }; + + gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_gmac_m2_ck>; + clock-mult = <1>; + clock-div = <2>; }; gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {