From patchwork Mon Oct 24 06:02:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mugunthan V N X-Patchwork-Id: 9391487 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 156FB607D0 for ; Mon, 24 Oct 2016 06:03:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 06BB828CC2 for ; Mon, 24 Oct 2016 06:03:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EEF6028CC8; Mon, 24 Oct 2016 06:03:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C49D928CC2 for ; Mon, 24 Oct 2016 06:03:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933204AbcJXGDK (ORCPT ); Mon, 24 Oct 2016 02:03:10 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:37812 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932970AbcJXGDI (ORCPT ); Mon, 24 Oct 2016 02:03:08 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id u9O62dkJ018769; Mon, 24 Oct 2016 01:02:39 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u9O62dDD026463; Mon, 24 Oct 2016 01:02:39 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Mon, 24 Oct 2016 01:02:38 -0500 Received: from a0131834lt.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u9O62Yel016221; Mon, 24 Oct 2016 01:02:35 -0500 From: Mugunthan V N To: Lee Jones CC: , Tony Lindgren , Jonathan Cameron , Vignesh R , , , , Sekhar Nori , Peter Ujfalusi , John Syne , Mugunthan V N Subject: [PATCH] drivers: mfd: ti_am335x_tscadc: increase ADC ref clock to 24MHz Date: Mon, 24 Oct 2016 11:32:26 +0530 Message-ID: <20161024060226.4170-1-mugunthanvnm@ti.com> X-Mailer: git-send-email 2.10.1.502.g6598894 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Increase ADC reference clock from 3MHz to 24MHz so that the sampling rates goes up from 100K samples per second to 800K samples per second on AM335x and AM437x SoC. Also increase opendelay for touchscreen configuration to equalize the increase in ADC reference clock frequency, which results in the same amount touch events reported via evtest on AM335x GP EVM. Signed-off-by: Mugunthan V N --- This patch depends on ADC DMA patch series [1] Without DMA support, when ADC ref clock is set at 24MHz, I am seeing fifo overflow as CPU is not able to pull the ADC samples. This answers that DMA support is must for ADC to consume the samples generated at 24MHz with no open, step delay or averaging with patch [2]. Measured the performance with the iio_generic_buffer with the patch [3] applied [1] - http://www.spinics.net/lists/devicetree/msg145045.html [2] - http://pastebin.ubuntu.com/23357935/ [3] - http://pastebin.ubuntu.com/23357939/ --- include/linux/mfd/ti_am335x_tscadc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h index b9a53e0..96c4207 100644 --- a/include/linux/mfd/ti_am335x_tscadc.h +++ b/include/linux/mfd/ti_am335x_tscadc.h @@ -90,7 +90,7 @@ /* Delay register */ #define STEPDELAY_OPEN_MASK (0x3FFFF << 0) #define STEPDELAY_OPEN(val) ((val) << 0) -#define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098) +#define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x500) #define STEPDELAY_SAMPLE_MASK (0xFF << 24) #define STEPDELAY_SAMPLE(val) ((val) << 24) #define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0) @@ -137,7 +137,7 @@ #define SEQ_STATUS BIT(5) #define CHARGE_STEP 0x11 -#define ADC_CLK 3000000 +#define ADC_CLK 24000000 #define TOTAL_STEPS 16 #define TOTAL_CHANNELS 8 #define FIFO1_THRESHOLD 19