From patchwork Thu Dec 1 23:34:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 9457303 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CD4BE60515 for ; Thu, 1 Dec 2016 23:34:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE915284ED for ; Thu, 1 Dec 2016 23:34:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A1100284E1; Thu, 1 Dec 2016 23:34:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C8D6284E1 for ; Thu, 1 Dec 2016 23:34:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759521AbcLAXeh (ORCPT ); Thu, 1 Dec 2016 18:34:37 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:37708 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757399AbcLAXeg (ORCPT ); Thu, 1 Dec 2016 18:34:36 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id uB1NYYdh002132; Thu, 1 Dec 2016 17:34:34 -0600 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id uB1NYYtV026620; Thu, 1 Dec 2016 17:34:34 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Thu, 1 Dec 2016 17:34:33 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id uB1NYXsV020033; Thu, 1 Dec 2016 17:34:33 -0600 Received: from localhost (uda0226610.am.dhcp.ti.com [128.247.83.173]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id uB1NYX300477; Thu, 1 Dec 2016 17:34:33 -0600 (CST) From: Grygorii Strashko To: "David S. Miller" , , Mugunthan V N CC: Sekhar Nori , , , Ivan Khoronzhuk , Grygorii Strashko Subject: [PATCH 1/7] net: ethernet: ti: cpdma: am437x: allow descs to be plased in ddr Date: Thu, 1 Dec 2016 17:34:26 -0600 Message-ID: <20161201233432.6182-2-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161201233432.6182-1-grygorii.strashko@ti.com> References: <20161201233432.6182-1-grygorii.strashko@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP It's observed that cpsw/cpdma is not working properly when CPPI descriptors are placed in DDR instead of internal CPPI RAM on am437x SoC: - rx/tx silently stops processing packets; - or - after boot it's working for sometime, but stuck once Network load is increased (ping is working, but iperf is not). (The same issue has not been reproduced on am335x and am57xx). It seems that write to HDP register processed faster by interconnect than writing of descriptor memory buffer in DDR, which is probably caused by store buffer / write buffer differences as these function are implemented differently across devices. So, to fix this i come up with two changes: 1) all accesses to the channel register HDP/CP/RXFREE registers should be done using sync IO accessors readl()/writel(), because all previous memory writes writes have to be completed before starting channel (write to HDP) or completing desc processing. 2) the change 1 only doesn't work on am437x and additional reading of desc's field is required right after the new descriptor was filled with data and before pointer on it will be stored in prev_desc->hw_next field or HDP register. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/davinci_cpdma.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c b/drivers/net/ethernet/ti/davinci_cpdma.c index c776e45..0924014 100644 --- a/drivers/net/ethernet/ti/davinci_cpdma.c +++ b/drivers/net/ethernet/ti/davinci_cpdma.c @@ -167,10 +167,10 @@ static struct cpdma_control_info controls[] = { /* various accessors */ #define dma_reg_read(ctlr, ofs) __raw_readl((ctlr)->dmaregs + (ofs)) -#define chan_read(chan, fld) __raw_readl((chan)->fld) +#define chan_read(chan, fld) readl((chan)->fld) #define desc_read(desc, fld) __raw_readl(&(desc)->fld) #define dma_reg_write(ctlr, ofs, v) __raw_writel(v, (ctlr)->dmaregs + (ofs)) -#define chan_write(chan, fld, v) __raw_writel(v, (chan)->fld) +#define chan_write(chan, fld, v) writel(v, (chan)->fld) #define desc_write(desc, fld, v) __raw_writel((u32)(v), &(desc)->fld) #define cpdma_desc_to_port(chan, mode, directed) \ @@ -1064,6 +1064,7 @@ int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data, desc_write(desc, sw_token, token); desc_write(desc, sw_buffer, buffer); desc_write(desc, sw_len, len); + desc_read(desc, sw_len); __cpdma_chan_submit(chan, desc);