From patchwork Fri Mar 17 01:48:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Rivshin X-Patchwork-Id: 9629617 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7AD2A60244 for ; Fri, 17 Mar 2017 02:21:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6B1CA28653 for ; Fri, 17 Mar 2017 02:21:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5FEF228677; Fri, 17 Mar 2017 02:21:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0969328653 for ; Fri, 17 Mar 2017 02:21:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752206AbdCQCVa (ORCPT ); Thu, 16 Mar 2017 22:21:30 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:53699 "EHLO out1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751081AbdCQCV3 (ORCPT ); Thu, 16 Mar 2017 22:21:29 -0400 Received: from compute7.internal (compute7.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id ED85120AA5; Thu, 16 Mar 2017 21:53:54 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute7.internal (MEProxy); Thu, 16 Mar 2017 21:53:54 -0400 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=awxrd.com; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=/ELJTZ YlLum1AQPpjcPnAY3Zei0=; b=MXCtsCZSNSPWwR1pbQclRLq+j6BBat3mfY7obh 21acMzLGSYJLtr7NnGJOe922iI04i7EVLMYOO4NBT9AmVBLjvUsAVNuobVLN0QEX uP0sObEJMdqe44tiJ8w+dmJvLgTBRS+hZba/1nNDd1JzV51dVdr/3DwHjMvoW5Uc EyREr/r6OSGvWmtxvoej1O9+VmsW070vKZd+AiAzPsHB5S+jj0aVWPtPq4XLeUNk txquYK/eQKkVcKyXYsMA2XmyTZcPLJrzcUfppITCpErgCuuEncI+BX/tJ05Fd3ml i1dIDRoFJZIKvB81LspT9L87fjyAFuNPQY+9Uz8SzMnzguyg== DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=/ELJTZYlLum1AQPpjcPnAY3Zei0=; b=LkknQlIV9 AeeMVzyd+NbIKhVARiVhg1vmgP7tUh0t+1lWKM9xzyUWB1vFFB401116xpAV6r+3 L3vZYOnOCna1GOuT8/tsRRhpH0kBfQjh0x54cBi+0YUozvpZhZ8Ot6CdyKHia7gT pq23q0gq3rvpgp9AlmeRuFSfh00eMsjxQBdyrnAjCDp1RkfK1xKBO3qk6LCz1z5O jRXnA5ucOJyWc001tBMm72gw15LkDJpHXHMU56nYaG6LwcgYREtxk0O/vP1bnr6i bAK7XS8h1tER4+aWY8/GfiQd4XzIOAWuQ/GNeg1hXr8devjKf3EM8DEcPvE7Q+Kc X0eV4BDZpxfdQ== X-ME-Sender: X-Sasl-enc: UqiZjMVy8ghsVNpU/KvXmYtNE0EHT1QiEPB1nS+Ha8Bg 1489715634 Received: from drivshin-linux.crosskeys.inscitek.com (unknown [24.213.148.66]) by mail.messagingengine.com (Postfix) with ESMTPA id 7A55424591; Thu, 16 Mar 2017 21:53:54 -0400 (EDT) From: David Rivshin To: linux-gpio@vger.kernel.org, linux-omap@vger.kernel.org, Grygorii Strashko Cc: Santosh Shilimkar , Kevin Hilman , Linus Walleij , Alexandre Courbot , linux-arm@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH 1/2] gpio: omap: return error if requested debounce time is not possible Date: Thu, 16 Mar 2017 21:48:55 -0400 Message-Id: <20170317014856.31449-2-drivshin@awxrd.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170317014856.31449-1-drivshin@awxrd.com> References: <20170317014856.31449-1-drivshin@awxrd.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: David Rivshin omap_gpio_debounce() does not validate that the requested debounce is within a range it can handle. Instead it lets the register value wrap silently, and always returns success. This can lead to all sorts of unexpected behavior, such as gpio_keys asking for a too-long debounce, but getting a very short debounce in practice. Fix this by returning -EINVAL if the requested value does not fit into the register field. If there is no debounce clock available at all, return -ENOTSUPP. Fixes: e85ec6c3047b ("gpio: omap: fix omap2_set_gpio_debounce") Cc: # 4.3+ Signed-off-by: David Rivshin --- drivers/gpio/gpio-omap.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index efc85a2..c40dbdd 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -208,9 +208,11 @@ static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) * OMAP's debounce time is in 31us steps * = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 * so we need to convert and round up to the closest unit. + * + * Return: 0 on success, negative error otherwise. */ -static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, - unsigned debounce) +static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, + unsigned debounce) { void __iomem *reg; u32 val; @@ -218,11 +220,12 @@ static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, bool enable = !!debounce; if (!bank->dbck_flag) - return; + return -ENOTSUPP; if (enable) { debounce = DIV_ROUND_UP(debounce, 31) - 1; - debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK; + if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) + return -EINVAL; } l = BIT(offset); @@ -255,6 +258,8 @@ static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, bank->context.debounce = debounce; bank->context.debounce_en = val; } + + return 0; } /** @@ -964,14 +969,15 @@ static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, { struct gpio_bank *bank; unsigned long flags; + int ret; bank = gpiochip_get_data(chip); raw_spin_lock_irqsave(&bank->lock, flags); - omap2_set_gpio_debounce(bank, offset, debounce); + ret = omap2_set_gpio_debounce(bank, offset, debounce); raw_spin_unlock_irqrestore(&bank->lock, flags); - return 0; + return ret; } static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,