From patchwork Mon Aug 21 23:48:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 9913951 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CDFA6602D8 for ; Mon, 21 Aug 2017 23:48:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BD5591FFB2 for ; Mon, 21 Aug 2017 23:48:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B20D023F88; Mon, 21 Aug 2017 23:48:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 427BF1FFB2 for ; Mon, 21 Aug 2017 23:48:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754158AbdHUXsv (ORCPT ); Mon, 21 Aug 2017 19:48:51 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:45842 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753979AbdHUXsu (ORCPT ); Mon, 21 Aug 2017 19:48:50 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7LNmORN028101; Mon, 21 Aug 2017 18:48:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503359304; bh=inoPa+gdh2gb6/1wYMLQTrf2VvtqyKSXqUVFvLKthDw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=G7Citpr25pErNtMt4Jl1dC+K3xQ3OUZ4+6U/WrVUyWtJsLLb8HqoaeaHJ4Tt4Dk59 OrwVyzXwFGTNwkaL5tuhkWSf6yC2JvEf+cpSD8mpnxVifFpym8NJUbgv9g5aWz/qp3 gIXTpORBbA5jiERIDBBNJEVA9dGdAZjyUGDBMNNo= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmOiX002365; Mon, 21 Aug 2017 18:48:24 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 21 Aug 2017 18:48:21 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 21 Aug 2017 18:48:21 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7LNmL5E003493; Mon, 21 Aug 2017 18:48:21 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v7LNmL307109; Mon, 21 Aug 2017 18:48:21 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Paul Walmsley , , , Tero Kristo , Suman Anna Subject: [PATCH 8/8] ARM: DRA7: hwmod_data: Add data for DSPs Date: Mon, 21 Aug 2017 18:48:18 -0500 Message-ID: <20170821234818.4755-9-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170821234818.4755-1-s-anna@ti.com> References: <20170821234818.4755-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DRA7xx family of SoCs can have up to two identical DSP processor subsystems, with most of them having a single DSP processor subsystem. The second DSP is present only on DRA74x and DRA76x variants currently. These subsystems are very similar to the respective processor subsystems on OMAP4/OMAP5 in terms of clock and reset integration. The relevant hwmod class and data structures are added for both the DSP remoteproc devices, with the data for DSP2 added only on DRA74x/DRA76x variants. Do note that these hwmod data structures do not have a .modulemode field as the devices are managed together with their corresponding MMUs. Each of the processor subsystem and its MMU are present within the same clock domain and requires the domain be clocked and enabled until the last entity is disabled. The module is disabled properly during the omap_device_idle processing of the MMU hwmod while disabling the MMU. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 66 +++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index e65a02855633..2a6341753c70 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -555,6 +555,53 @@ static struct omap_hwmod dra7xx_tptc1_hwmod = { }; /* + * 'dsp' class + * dsp sub-system + */ + +static struct omap_hwmod_class dra7xx_dsp_hwmod_class = { + .name = "dsp", +}; + +static struct omap_hwmod_rst_info dra7xx_dsp_resets[] = { + { .name = "dsp", .rst_shift = 0 }, +}; + +/* dsp1 processor */ +static struct omap_hwmod dra7xx_dsp1_hwmod = { + .name = "dsp1", + .class = &dra7xx_dsp_hwmod_class, + .clkdm_name = "dsp1_clkdm", + .rst_lines = dra7xx_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET, + }, + }, +}; + +/* dsp2 processor */ +static struct omap_hwmod dra7xx_dsp2_hwmod = { + .name = "dsp2", + .class = &dra7xx_dsp_hwmod_class, + .clkdm_name = "dsp2_clkdm", + .rst_lines = dra7xx_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'dss' class * */ @@ -3266,6 +3313,22 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = { .user = OCP_USER_MPU, }; +/* dsp1 -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_dsp1__l3_main_1 = { + .master = &dra7xx_dsp1_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dsp2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_dsp2__l3_main_1 = { + .master = &dra7xx_dsp2_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_1 -> dss */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = { .master = &dra7xx_l3_main_1_hwmod, @@ -4215,6 +4278,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__tptc1, &dra7xx_l3_main_1__dss, &dra7xx_l3_main_1__dispc, + &dra7xx_dsp1__l3_main_1, &dra7xx_l3_main_1__hdmi, &dra7xx_l3_main_1__aes1, &dra7xx_l3_main_1__aes2, @@ -4326,6 +4390,7 @@ static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__usb_otg_ss4, &dra7xx_l3_main_1__mmu0_dsp2, &dra7xx_l3_main_1__mmu1_dsp2, + &dra7xx_dsp2__l3_main_1, NULL, }; @@ -4333,6 +4398,7 @@ static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__usb_otg_ss4, &dra7xx_l3_main_1__mmu0_dsp2, &dra7xx_l3_main_1__mmu1_dsp2, + &dra7xx_dsp2__l3_main_1, NULL, };