From patchwork Tue Oct 10 10:16:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 9995699 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3452760230 for ; Tue, 10 Oct 2017 10:17:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B82928473 for ; Tue, 10 Oct 2017 10:17:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 205F128478; Tue, 10 Oct 2017 10:17:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA2ED28473 for ; Tue, 10 Oct 2017 10:17:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751420AbdJJKQu (ORCPT ); Tue, 10 Oct 2017 06:16:50 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:32510 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755871AbdJJKQW (ORCPT ); Tue, 10 Oct 2017 06:16:22 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9AAGHsD023842; Tue, 10 Oct 2017 05:16:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507630577; bh=/Z+kTpajQhSfkRmVd7pqZCx1dFCAqF8vjBEsFpH9i2M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tNMGM4KcxCcNnhDOUXjhvE4bNYdtlQ1zXGpNNPAVoGF0R5aeB0PYyRlTyVZR4kpKI /9xBoO3G7vJ5AbdXyiSjuO3+zP+68AgZXfYijw1Mkue73a9Uv3Bi+TOtFh814gOuMK n/R5FE4KqGvJlMxlGuDVp4VUoa9VXN40JkkNtGXQ= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAGHU0006454; Tue, 10 Oct 2017 05:16:17 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 10 Oct 2017 05:16:17 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 10 Oct 2017 05:16:17 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAG8uj025359; Tue, 10 Oct 2017 05:16:14 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Mark Rutland CC: Kishon Vijay Abraham I , , , , , Subject: [PATCH 2/4] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 Date: Tue, 10 Oct 2017 15:46:04 +0530 Message-ID: <20171010101606.15951-3-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171010101606.15951-1-kishon@ti.com> References: <20171010101606.15951-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add syscon properties required for configuring PCIe in x2 lane mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- Documentation/devicetree/bindings/pci/ti-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 82cb875e4cec..455cb74a475c 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -13,6 +13,10 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", where is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt + - syscon-lane-conf : phandle/offset pair. Phandle to the system control module and the + register offset to specify 1 lane or 2 lane. + - syscon-lane-sel : phandle/offset pair. Phandle to the system control module and the + register offset to specify lane selection. HOST MODE =========