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[73.65.120.235]) by smtp.gmail.com with ESMTPSA id d16-v6sm5320732iob.74.2018.05.18.21.15.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 May 2018 21:15:35 -0700 (PDT) From: Adam Ford To: linux-omap@vger.kernel.org Cc: tony@atomide.com, t-kristo@ti.com, Adam Ford Subject: [RFC] ARM: dts: am3517-evm: Enable MUSB OTG Controller Date: Fri, 18 May 2018 23:15:27 -0500 Message-Id: <20180519041527.28308-1-aford173@gmail.com> X-Mailer: git-send-email 2.17.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to the schematic, the USB0_DP/DM pins are used for the USB0. According to the AM3517 datasheet, "This mux selection is controlled by CONTROL_DEVCONF2 register" The pdata-quirks section sets up this register based on the ti kernel 3.8 for the am3517-evm. The device tree section disables the default omap3 and enables the am3517 variation RFC: When we modprobe g_zero to use the OTG port as host, we're still getting errors: udc-core: couldn't find an available UDC - added [zero] to list of pending drivers I was hoping someome might have some insight as to what to try. Signed-off-by: Adam Ford diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index 135f38e6f6e2..191f60e4475f 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -169,6 +169,18 @@ #pwm-cells = <3>; }; + usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&otg_drv_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + startup-delay-us = <70000>; + gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; /* gpio_125 */ + }; + hsusb1_phy: hsusb1_phy { compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ @@ -243,6 +255,15 @@ phys = <&hsusb1_phy>; }; +&usb_otg_hs { + status = "disabled"; +}; + +&am35x_otg_hs { + status = "okay"; + vbus-supply = <&usb0_vbus>; +}; + &omap3_pmx_core { pinctrl-names = "default"; pinctrl-0 = <&hsusb1_reset_pins>; @@ -305,6 +326,12 @@ >; }; + otg_drv_vbus: pinmux_otg_drv_vbus { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2210, PIN_OUTPUT | MUX_MODE4) /* usb0_drvvbus.gpio_125 */ + >; + }; + hsusb1_reset_pins: pinmux_hsusb1_reset_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 6459816c2879..b3a31fbf793f 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -262,6 +262,17 @@ static void __init omap3_sbc_t3517_legacy_init(void) static void __init am3517_evm_legacy_init(void) { + unsigned int devconf2; + /* + * Set up USB clock/mode in the DEVCONF2 register. + */ + devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); + /* USB2.0 PHY reference clock is 13 MHz */ + devconf2 &= ~(CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE); + devconf2 |= CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | CONF2_VBDTCTEN + | CONF2_DATPOL; + omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); + am35xx_emac_reset(); }