| Message ID | 20191002120611.26121-5-t-kristo@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: ti: re-work divider clock support | expand |
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi index e66fc57ec35d..4e9cc9003594 100644 --- a/arch/arm/boot/dts/omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi @@ -105,3 +105,7 @@ <&mcbsp4_ick>, <&uart4_fck>; }; }; + +&dpll4_m4_ck { + ti,max-div = <31>; +}; diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 685c82a9d03e..0656c32439d2 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -416,7 +416,7 @@ #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll4_ck>; - ti,max-div = <32>; + ti,max-div = <16>; reg = <0x0e40>; ti,index-starts-at-one; };
The maximum divider value for DPLL4 M4 divider appears wrong. For most OMAP3 family SoCs this is 16, but it is defined as 32, which is maybe only valid for omap36xx. To avoid any overflows in trying to write this register, set the max to 16 for all omap3 family, except omap36xx. For omap36xx the maximum is set to 31, as it appears value 32 is not working properly. Signed-off-by: Tero Kristo <t-kristo@ti.com> --- arch/arm/boot/dts/omap36xx-clocks.dtsi | 4 ++++ arch/arm/boot/dts/omap3xxx-clocks.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-)