From patchwork Thu Oct 10 08:21:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 11182863 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C399139A for ; Thu, 10 Oct 2019 08:21:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 737522067B for ; Thu, 10 Oct 2019 08:21:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VrH5ZIqJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733171AbfJJIVW (ORCPT ); Thu, 10 Oct 2019 04:21:22 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:41350 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733170AbfJJIVW (ORCPT ); Thu, 10 Oct 2019 04:21:22 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9A8LHw2124191; Thu, 10 Oct 2019 03:21:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570695677; bh=Ivfa6xStCW1FR0q2GN3mF+HPXnlsXQHMTyczYoiOtus=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VrH5ZIqJBeBCsmm77xjciQ7WfGg+X8gxsepYkVfurLQnpmqudOdAAhus+dV+GplfF HoXrF0efNo2vsP9G3WZIgl/iSIAd4TQ5BQCSiRvLQtqdek92DgAoEXM6phbD4e3Lq7 joZeMtCj6WcGBBgbzm+0COQo2+RAOQHF5f/dDcu8= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9A8LHAZ003574 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 10 Oct 2019 03:21:17 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 10 Oct 2019 03:21:16 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 10 Oct 2019 03:21:16 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9A8LAtD012630; Thu, 10 Oct 2019 03:21:15 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 3/5] ARM: dts: am33xx: Add PRM data Date: Thu, 10 Oct 2019 11:21:06 +0300 Message-ID: <20191010082108.15448-4-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191010082108.15448-1-t-kristo@ti.com> References: <20191010082108.15448-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add PRM data for AM33xx SoC. Initially this is used to provide reset support, but will be expanded later to support also powerdomain control. Signed-off-by: Tero Kristo --- arch/arm/boot/dts/am33xx.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index fb6b8aa12cc5..33b3346e4769 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -465,3 +465,29 @@ #include "am33xx-l4.dtsi" #include "am33xx-clocks.dtsi" + +&prcm { + prm_per: prm@c00 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0xc00 0x100>; + #reset-cells = <1>; + }; + + prm_wkup: prm@d00 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0xd00 0x100>; + #reset-cells = <1>; + }; + + prm_device: prm@f00 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0xf00 0x100>; + #reset-cells = <1>; + }; + + prm_gfx: prm@1100 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0x1100 0x100>; + #reset-cells = <1>; + }; +};