From patchwork Wed Mar 4 09:00:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 11419609 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2A32992A for ; Wed, 4 Mar 2020 09:01:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 06EED2166E for ; Wed, 4 Mar 2020 09:01:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="EZ0jXAZC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728909AbgCDJA5 (ORCPT ); Wed, 4 Mar 2020 04:00:57 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:44212 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728387AbgCDJA5 (ORCPT ); Wed, 4 Mar 2020 04:00:57 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02490k32090738; Wed, 4 Mar 2020 03:00:46 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1583312447; bh=ha9OQnDcooAmHEgCcB9O6rbxK86frAqOmsgVJJ3RY+E=; h=From:To:CC:Subject:Date; b=EZ0jXAZCXO4y5aS1mftire1uwF1aP/rNpADio3gg6IYo11C3tJkqKyRKbwq4xj6tB vkhAiAAZPeQT7bd6PIx8FDbT3wL7QVHsaD/ENqGv7zlkmRIFKcPQ7B0QNwP7dFpW68 uBVVPc0KZaTNwNCzSp3RglAAQSLfkC54VdhSgcrk= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02490kSf126521 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 4 Mar 2020 03:00:46 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Wed, 4 Mar 2020 03:00:46 -0600 Received: from localhost.localdomain (10.64.41.19) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Wed, 4 Mar 2020 03:00:46 -0600 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by localhost.localdomain (8.15.2/8.15.2) with ESMTP id 02490hm9093867; Wed, 4 Mar 2020 03:00:43 -0600 From: Roger Quadros To: CC: , , , , Roger Quadros , Christoph Hellwig , Robin Murphy , Rob Herring Subject: [PATCH] dra7: sata: Fix SATA with CONFIG_ARM_LPAE enabled Date: Wed, 4 Mar 2020 11:00:31 +0200 Message-ID: <20200304090031.30360-1-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Even though the TRM says that SATA IP has 36 address bits wired in the SoC, we see bus errors whenever any address greater than 32-bit is given to the controller. This happens on dra7-EVM with 4G of RAM with CONFIG_ARM_LPAE=y. As a workaround we limit the DMA address range to 32-bits for SATA. Cc: Christoph Hellwig Cc: Robin Murphy Cc: Rob Herring Reported-by: Yan Liu Signed-off-by: Roger Quadros --- NOTE: Currently ARM dma-mapping code doesn't account for devices bus_dma_limit. This is fixed in [1]. [1] https://lkml.org/lkml/2020/2/18/712 arch/arm/boot/dts/dra7.dtsi | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d78b684e7fca..895462c22d1c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -642,15 +642,22 @@ }; /* OCP2SCP3 */ - sata: sata@4a141100 { - compatible = "snps,dwc-ahci"; - reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; - interrupts = ; - phys = <&sata_phy>; - phy-names = "sata-phy"; - clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; - ti,hwmods = "sata"; - ports-implemented = <0x1>; + sata_aux_bus { + #address-cells = <1>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges = <0x0 0x4a140000 0x0 0x1200>; + dma-ranges = <0x0 0x0 0x1 0x00000000>; + sata: sata@4a141100 { + compatible = "snps,dwc-ahci"; + reg = <0x0 0x0 0x1100>, <0x1100 0x0 0x7>; + interrupts = ; + phys = <&sata_phy>; + phy-names = "sata-phy"; + clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; + ti,hwmods = "sata"; + ports-implemented = <0x1>; + }; }; /* OCP2SCP1 */