Message ID | 20240730092353.10209-1-d.haller@phytec.de (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | [v2,1/2] ARM: dts: ti: omap: am335x-regor: Fix RS485 settings | expand |
On Tue, 30 Jul 2024 11:23:52 +0200, Dominik Haller wrote: > RTS pin seems to have inverted behavior on am335x, other than expected > with default "rs485-rts-active-high" (instead of low on idle, high on send, > it is the opposite). Transceiver datasheet also suggests a pulldown. > Add includes to pin definitions that are used. > > Applied, thanks! [1/2] ARM: dts: ti: omap: am335x-regor: Fix RS485 settings commit: e589ec9847e5fc78a219a85b740599ae115b6431 [2/2] ARM: dts: ti: omap: am335x-wega: Fix audio clock provider commit: 6a410ff5359610779908cf94f18f9f39281ecabd Best regards,
diff --git a/arch/arm/boot/dts/ti/omap/am335x-regor.dtsi b/arch/arm/boot/dts/ti/omap/am335x-regor.dtsi index 625db3bcd365..287d209a0ea9 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-regor.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-regor.dtsi @@ -5,6 +5,9 @@ * */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/am33xx.h> + / { model = "Phytec AM335x phyBOARD-REGOR"; compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"; @@ -188,7 +191,7 @@ uart1_rs485_pins: pinmux-uart1-rs485-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; }; @@ -198,4 +201,9 @@ &uart1 { pinctrl-0 = <&uart1_rs485_pins>; status = "okay"; linux,rs485-enabled-at-boot-time; + /* + * un-intuitively, yet with the default (active-high), + * am335x RTS is high on idle and gets low on active ! + */ + rs485-rts-active-low; };