From patchwork Wed May 18 23:36:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gerlach X-Patchwork-Id: 9123041 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 61B5DBF440 for ; Wed, 18 May 2016 23:37:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 81DB120306 for ; Wed, 18 May 2016 23:37:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8697720328 for ; Wed, 18 May 2016 23:37:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752288AbcERXhU (ORCPT ); Wed, 18 May 2016 19:37:20 -0400 Received: from arroyo.ext.ti.com ([198.47.19.12]:59315 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752215AbcERXhQ (ORCPT ); Wed, 18 May 2016 19:37:16 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u4INamuN017968; Wed, 18 May 2016 18:36:48 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u4INamMi002179; Wed, 18 May 2016 18:36:48 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Wed, 18 May 2016 18:36:47 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u4INalnZ030371; Wed, 18 May 2016 18:36:47 -0500 Received: from localhost (uda0274052.am.dhcp.ti.com [128.247.83.19]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id u4INal319655; Wed, 18 May 2016 18:36:47 -0500 (CDT) From: Dave Gerlach To: , , , , Tony Lindgren CC: Viresh Kumar , Rob Herring , Mark Rutland , Nishanth Menon , Yegor Yefremov , Dave Gerlach Subject: [PATCH 8/8] ARM: dts: dra7: Move to operating-points-v2 table Date: Wed, 18 May 2016 18:36:33 -0500 Message-ID: <20af92f75bf0f707458dd021719cce3a70d768d5.1463606963.git.d-gerlach@ti.com> X-Mailer: git-send-email 2.7.3 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add an operating-points-v2 table with all OPPs available for all silicon revisions along with necessary data for use by ti-opp driver to selectively enable the appropriate OPPs at runtime and handle voltage transitions As we now need to define voltage ranges for each OPP, we define the minimum and maximum voltage to match the ranges possible for AVS class0 voltage as defined by the DRA7/AM57 Data Manual, with the exception of using a range for OPP_OD based on historical data to ensure that SoCs from older lots still continue to boot, even though more optimal voltages are now the standard. Once an AVS Class0 driver is in place it will be possible for these OPP voltages to be adjusted to any voltage within the provided range. Information from SPRS953, Revised December 2015. Signed-off-by: Dave Gerlach --- arch/arm/boot/dts/dra7.dtsi | 26 +++++++++++++++++++++----- arch/arm/boot/dts/dra74x.dtsi | 1 + 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 104b62657163..0d74f8a15937 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -82,11 +82,9 @@ compatible = "arm,cortex-a15"; reg = <0>; - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; + operating-points-v2 = <&cpu0_opp_table>; + ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>; + ti,syscon-rev = <&scm_wkup 0x204>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -100,6 +98,24 @@ }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp_nom@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1060000 850000 1150000>; + opp-supported-hw = <0xFF 0x01>; + opp-suspend; + }; + + opp_od@1176000000 { + opp-hz = /bits/ 64 <1176000000>; + opp-microvolt = <1160000 885000 1160000>; + opp-supported-hw = <0xFF 0x02>; + }; + }; + /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 0c31db3a8919..0a8a5eee5dd0 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -17,6 +17,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; + operating-points-v2 = <&cpu0_opp_table>; }; };