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[1/2] ARM: l2x0: Errata fix for flush by Wayoperationcan cause data corruption

Message ID 491849bc08797fc8c4d0def52dd6308a@mail.gmail.com (mailing list archive)
State Awaiting Upstream, archived
Headers show

Commit Message

Santosh Shilimkar March 7, 2011, 12:25 p.m. UTC
None
diff mbox

Patch

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 65ea7bb..ef41f7e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1135,7 +1135,7 @@  config ARM_ERRATA_742231

 config PL310_ERRATA_588369
 	bool "Clean & Invalidate maintenance operations do not invalidate
clean lines"
-	depends on CACHE_L2X0 && ARCH_OMAP4
+	depends on CACHE_L2X0
 	help
 	   The PL310 L2 cache controller implements three types of Clean &
 	   Invalidate maintenance operations: by Physical Address
@@ -1144,8 +1144,7 @@  config PL310_ERRATA_588369
 	   clean operation followed immediately by an invalidate
operation,
 	   both performing to the same memory location. This functionality
 	   is not correctly implemented in PL310 as clean lines are not
-	   invalidated as a result of these operations. Note that this
errata
-	   uses Texas Instrument's secure monitor api.
+	   invalidated as a result of these operations.

 config ARM_ERRATA_720789
 	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can
broadcast a faulty ASID"
@@ -1172,6 +1171,16 @@  config ARM_ERRATA_743622
 	  visible impact on the overall performance or power consumption
of the
 	  processor.

+config PL310_ERRATA_727915
+	bool "Background Clean & Invalidate by Way operation can cause
data corruption"
+	depends on CACHE_L2X0
+	help
+	  PL310 implements the Clean & Invalidate by Way L2 cache
maintenance
+	  operation (offset 0x7FC). This operation runs in background so
that
+	  PL310 can handle normal accesses while it is in progress. Under
very
+	  rare circumstances, due to this erratum, write data can be lost
when
+	  PL310 treats a cacheable write transaction during a Clean &
+	  Invalidate by Way operation.
 endmenu

 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index fc19009..348d513 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -31,6 +31,7 @@  struct outer_cache_fns {
 #ifdef CONFIG_OUTER_CACHE_SYNC
 	void (*sync)(void);
 #endif
+	void (*set_debug)(unsigned long);
 };

 #ifdef CONFIG_OUTER_CACHE
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb..0986cce 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -67,18 +67,24 @@  static inline void l2x0_inv_line(unsigned long addr)
 	writel_relaxed(addr, base + L2X0_INV_LINE_PA);
 }

-#ifdef CONFIG_PL310_ERRATA_588369
-static void debug_writel(unsigned long val)
-{
-	extern void omap_smc1(u32 fn, u32 arg);
+#if defined(CONFIG_PL310_ERRATA_588369) ||
defined(CONFIG_PL310_ERRATA_727915)

-	/*
-	 * Texas Instrument secure monitor api to modify the
-	 * PL310 Debug Control Register.
-	 */
-	omap_smc1(0x100, val);
+#define debug_writel(val)	outer_cache.set_debug(val)
+
+static void l2x0_set_debug(unsigned long val)
+{
+	writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
 }
+#else
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
+}
+
+#define l2x0_set_debug	NULL
+#endif

+#ifdef CONFIG_PL310_ERRATA_588369
 static inline void l2x0_flush_line(unsigned long addr)
 {