From patchwork Thu Feb 18 10:45:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemanth V X-Patchwork-Id: 80240 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o1IAjdPe028101 for ; Thu, 18 Feb 2010 10:45:40 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756721Ab0BRKpj (ORCPT ); Thu, 18 Feb 2010 05:45:39 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:58687 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756515Ab0BRKpi (ORCPT ); Thu, 18 Feb 2010 05:45:38 -0500 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o1IAjSTk001252 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 18 Feb 2010 04:45:28 -0600 Received: from dbdmail.itg.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id o1IAjPVB019188; Thu, 18 Feb 2010 04:45:26 -0600 (CST) Received: from 10.24.255.18 (SquirrelMail authenticated user x0099946); by dbdmail.itg.ti.com with HTTP; Thu, 18 Feb 2010 16:15:27 +0530 (IST) Message-ID: <49574.10.24.255.18.1266489927.squirrel@dbdmail.itg.ti.com> Date: Thu, 18 Feb 2010 16:15:27 +0530 (IST) Subject: [RESEND] [PATCH V2 2/3]: Adds support for FIFO From: "Hemanth V" To: grant.likely@secretlab.ca Cc: linux-omap@vger.kernel.org, spi-devel-general@lists.sourceforge.net User-Agent: SquirrelMail/1.4.3a X-Mailer: SquirrelMail/1.4.3a MIME-Version: 1.0 X-Priority: 3 (Normal) Importance: Normal Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 18 Feb 2010 10:45:40 +0000 (UTC) diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index 715c518..75a3f04 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c @@ -37,10 +37,11 @@ #include #include +#include #define OMAP2_MCSPI_MAX_FREQ 48000000 - +#define OMAP2_MCSPI_MAX_FIFODEPTH 64 /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */ #define OMAP2_MCSPI_MAX_CTRL 4 @@ -52,6 +53,7 @@ #define OMAP2_MCSPI_WAKEUPENABLE 0x20 #define OMAP2_MCSPI_SYST 0x24 #define OMAP2_MCSPI_MODULCTRL 0x28 +#define OMAP2_MCSPI_XFERLEVEL 0x7c /* per-channel banks, 0x14 bytes each, first is: */ #define OMAP2_MCSPI_CHCONF0 0x2c @@ -88,11 +90,15 @@ #define OMAP2_MCSPI_CHCONF_IS BIT(18) #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) +#define OMAP2_MCSPI_CHCONF_FFET BIT(27) +#define OMAP2_MCSPI_CHCONF_FFER BIT(28) #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) +#define OMAP2_MCSPI_IRQ_EOW BIT(17) + #define OMAP2_MCSPI_CHCTRL_EN BIT(0) #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) @@ -128,6 +134,10 @@ struct omap2_mcspi { unsigned long phys; /* SPI1 has 4 channels, while SPI2 has 2 */ struct omap2_mcspi_dma *dma_channels; + u8 mcspi_mode; + u8 dma_mode; + u8 force_cs_mode; + u16 fifo_depth; }; struct omap2_mcspi_cs { @@ -151,6 +161,37 @@ struct omap2_mcspi_regs { static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL]; +#ifdef CONFIG_SPI_DEBUG +struct reg_type { + char name[40]; + int offset; +}; + +static struct reg_type reg_map[] = { + {"MCSPI_REV", 0x0}, + {"MCSPI_SYSCONFIG", 0x10}, + {"MCSPI_SYSSTATUS", 0x14}, + {"MCSPI_IRQSTATUS", 0x18}, + {"MCSPI_IRQENABLE", 0x1C}, + {"MCSPI_WAKEUPENABLE", 0x20}, + {"MCSPI_SYST", 0x24}, + {"MCSPI_MODULCTRL", 0x28}, + {"MCSPI_XFERLEVEL", 0x7c}, + {"CH0", 0x2C}, + {"CH1", 0x40}, + {"CH2", 0x54}, + {"CH3", 0x68} +}; + +static struct reg_type ch_reg_type[] = { + {"CONF", 0x00}, + {"STAT", 0x04}, + {"CTRL", 0x08}, + {"TX", 0x0C}, + {"RX", 0x10}, +}; +#endif + static struct workqueue_struct *omap2_mcspi_wq; #define MOD_REG_BIT(val, mask, set) do { \ @@ -221,6 +262,39 @@ static void omap2_mcspi_set_dma_req(const struct spi_device *spi, mcspi_write_chconf0(spi, l); } +#ifdef CONFIG_SPI_DEBUG +static int +omap2_mcspi_dump_regs(struct spi_master *master) +{ + u32 spi_base; + u32 reg; + u32 channel; + struct omap2_mcspi *mcspi = spi_master_get_devdata(master); + + spi_base = (u32)mcspi->base; + + for (reg = 0; (reg < ARRAY_SIZE(reg_map)); reg++) { + struct reg_type *reg_d = ®_map[reg]; + u32 base1 = spi_base + reg_d->offset; + if (reg_d->name[0] == 'C') { + for (channel = 0; (channel < (ARRAY_SIZE(ch_reg_type))); + channel++) { + struct reg_type *reg_c = &ch_reg_type[channel]; + u32 base2 = base1 + reg_c->offset; + pr_debug("MCSPI_%s%s [0x%08X] = 0x%08X\n", + reg_d->name, reg_c->name, base2, + __raw_readl(base2)); + } + } else { + pr_debug("%s : [0x%08X] = 0x%08X\n", + reg_d->name, base1, __raw_readl(base1)); + } + + } + return 0; +} +#endif + static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) {