From patchwork Tue Oct 8 22:05:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 3005501 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 241689F3EF for ; Tue, 8 Oct 2013 22:05:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CD7E9201EF for ; Tue, 8 Oct 2013 22:05:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 99C4C201B8 for ; Tue, 8 Oct 2013 22:05:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755264Ab3JHWFx (ORCPT ); Tue, 8 Oct 2013 18:05:53 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:48829 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753397Ab3JHWFw (ORCPT ); Tue, 8 Oct 2013 18:05:52 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r98M5OFp018748; Tue, 8 Oct 2013 17:05:24 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r98M5OT9031647; Tue, 8 Oct 2013 17:05:24 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Tue, 8 Oct 2013 17:05:24 -0500 Received: from [158.218.103.117] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id r98M5MhV009876; Tue, 8 Oct 2013 17:05:22 -0500 Message-ID: <525481A2.4020900@ti.com> Date: Tue, 8 Oct 2013 18:05:22 -0400 From: Santosh Shilimkar User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/17.0 Thunderbird/17.0 MIME-Version: 1.0 To: Tony Lindgren , Sricharan R CC: , , , , , Subject: Re: [PATCH V4] ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register References: <1379520162-31932-1-git-send-email-r.sricharan@ti.com> <524D44B9.30208@ti.com> <20131008214523.GU8313@atomide.com> In-Reply-To: <20131008214523.GU8313@atomide.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Tuesday 08 October 2013 05:45 PM, Tony Lindgren wrote: > * Sricharan R [131003 03:27]: >> On Wednesday 18 September 2013 09:32 PM, Sricharan R wrote: >>> --- a/arch/arm/boot/dts/omap5.dtsi >>> +++ b/arch/arm/boot/dts/omap5.dtsi >>> @@ -52,7 +52,6 @@ >>> , >>> , >>> ; >>> - clock-frequency = <6144000>; >>> }; >>> >>> gic: interrupt-controller@48211000 { > > Can the above be done later on in a separate clean-up patch? > If so I can drop that part as that removes a dependency to the > .dts patches queued by Benoit. > This can be applied separately. >>> --- a/arch/arm/mach-omap2/omap-smp.c >>> +++ b/arch/arm/mach-omap2/omap-smp.c >>> @@ -41,6 +41,8 @@ >>> >>> u16 pm44xx_errata; >>> >>> +extern unsigned long arch_timer_freq; >>> + >>> /* SCU base address */ >>> static void __iomem *scu_base; >>> > > No externs in *.c files please, checkpatch.pl and sparse should warn > about this. > >> Are you planning to pull this patch and the below $subject patch as well? They are >> acked and tested. >> >> ARM: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk frequency >> >> http://www.spinics.net/lists/linux-omap/msg97281.html > > The 20MHz patch I've applied, just noticed the above things > when was about to apply this. > Now re-looking at the patch, I think this extern stuff can be and should be avoided. It needs order change though like below. Not tested but should work. Then, the CNTFREQ programming needs to be moved to realtime_counter_init(). It should be actually part of that first place instead of timer_init(). On secondary CPU then a simple asm accessor can read the CNTFREQ and pass that to SMC. Sricharan, Can you try above and see if everything works as expected. If it does, please post an updated patch based on above. Regards, santosh --- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index fa74a06..c8d8308 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -631,10 +631,9 @@ void __init omap4_local_timer_init(void) #ifdef CONFIG_SOC_OMAP5 void __init omap5_realtime_timer_init(void) { - omap4_sync32k_timer_init(); realtime_counter_init(); - clocksource_of_init(); + omap4_sync32k_timer_init(); } #endif /* CONFIG_SOC_OMAP5 */