From patchwork Wed Mar 18 09:55:19 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 12811 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n2I9tNIE027942 for ; Wed, 18 Mar 2009 09:55:32 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754868AbZCRJzc (ORCPT ); Wed, 18 Mar 2009 05:55:32 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1754435AbZCRJzc (ORCPT ); Wed, 18 Mar 2009 05:55:32 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:35449 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754868AbZCRJzc convert rfc822-to-8bit (ORCPT ); Wed, 18 Mar 2009 05:55:32 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id n2I9tL86029305 for ; Wed, 18 Mar 2009 04:55:27 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id n2I9tLWx022071 for ; Wed, 18 Mar 2009 15:25:21 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Wed, 18 Mar 2009 15:25:21 +0530 From: "Nayak, Rajendra" To: "linux-omap@vger.kernel.org" CC: "Nayak, Rajendra" Date: Wed, 18 Mar 2009 15:25:19 +0530 Subject: [PATCH 01/05] OMAP3: SR: Fix init voltage on OPP change Thread-Topic: [PATCH 01/05] OMAP3: SR: Fix init voltage on OPP change Thread-Index: Acmnr6WkboqJNlEcQt+L6/5j5eKsKw== Message-ID: <5A47E75E594F054BAF48C5E4FC4B92AB02FAEDE848@dbde02.ent.ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Rajendra Nayak This patch fixes a bug wherein the inital voltage was not set correctly on a OPP change Signed-off-by: Rajendra Nayak Signed-off-by: Jouni Hogander --- arch/arm/mach-omap2/smartreflex.c | 39 ++++++++++++++++++++++++++++++++++---- 1 files changed, 35 insertions(+), 4 deletions(-) To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux-omap-2.6/arch/arm/mach-omap2/smartreflex.c =================================================================== --- linux-omap-2.6.orig/arch/arm/mach-omap2/smartreflex.c 2009-03-18 13:56:15.900545736 +0530 +++ linux-omap-2.6/arch/arm/mach-omap2/smartreflex.c 2009-03-18 13:56:24.906271669 +0530 @@ -30,6 +30,7 @@ #include #include #include +#include #include "prm.h" #include "smartreflex.h" @@ -183,7 +184,6 @@ static void sr_set_efuse_nvalues(struct sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & OMAP343X_SR1_SENNENABLE_MASK) >> OMAP343X_SR1_SENNENABLE_SHIFT; - sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & OMAP343X_SR1_SENPENABLE_MASK) >> OMAP343X_SR1_SENPENABLE_SHIFT; @@ -364,7 +364,9 @@ static void sr_configure(struct omap_sr static int sr_enable(struct omap_sr *sr, u32 target_opp_no) { - u32 nvalue_reciprocal; + u32 nvalue_reciprocal, v; + + BUG_ON(!(mpu_opps && l3_opps)); sr->req_opp_no = target_opp_no; @@ -418,14 +420,43 @@ static int sr_enable(struct omap_sr *sr, sr_modify_reg(sr, ERRCONFIG, (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST), (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST)); + if (sr->srid == SR1) { + /* set/latch init voltage */ + v = prm_read_mod_reg(OMAP3430_GR_MOD, + OMAP3_PRM_VP1_CONFIG_OFFSET); + v &= ~(OMAP3430_INITVOLTAGE_MASK | OMAP3430_INITVDD); + v |= mpu_opps[target_opp_no].vsel << + OMAP3430_INITVOLTAGE_SHIFT; + prm_write_mod_reg(v, OMAP3430_GR_MOD, + OMAP3_PRM_VP1_CONFIG_OFFSET); + /* write1 to latch */ + prm_set_mod_reg_bits(OMAP3430_INITVDD, OMAP3430_GR_MOD, + OMAP3_PRM_VP1_CONFIG_OFFSET); + /* write2 clear */ + prm_clear_mod_reg_bits(OMAP3430_INITVDD, OMAP3430_GR_MOD, + OMAP3_PRM_VP1_CONFIG_OFFSET); /* Enable VP1 */ prm_set_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD, - OMAP3_PRM_VP1_CONFIG_OFFSET); + OMAP3_PRM_VP1_CONFIG_OFFSET); } else if (sr->srid == SR2) { + /* set/latch init voltage */ + v = prm_read_mod_reg(OMAP3430_GR_MOD, + OMAP3_PRM_VP2_CONFIG_OFFSET); + v &= ~(OMAP3430_INITVOLTAGE_MASK | OMAP3430_INITVDD); + v |= l3_opps[target_opp_no].vsel << + OMAP3430_INITVOLTAGE_SHIFT; + prm_write_mod_reg(v, OMAP3430_GR_MOD, + OMAP3_PRM_VP2_CONFIG_OFFSET); + /* write1 to latch */ + prm_set_mod_reg_bits(OMAP3430_INITVDD, OMAP3430_GR_MOD, + OMAP3_PRM_VP2_CONFIG_OFFSET); + /* write2 clear */ + prm_clear_mod_reg_bits(OMAP3430_INITVDD, OMAP3430_GR_MOD, + OMAP3_PRM_VP2_CONFIG_OFFSET); /* Enable VP2 */ prm_set_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD, - OMAP3_PRM_VP2_CONFIG_OFFSET); + OMAP3_PRM_VP2_CONFIG_OFFSET); } /* SRCONFIG - enable SR */--