From patchwork Thu Aug 12 14:51:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sanjeev Premi X-Patchwork-Id: 119272 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o7CEpHCd003579 for ; Thu, 12 Aug 2010 14:51:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753727Ab0HLOvQ (ORCPT ); Thu, 12 Aug 2010 10:51:16 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:59768 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751643Ab0HLOvQ convert rfc822-to-8bit (ORCPT ); Thu, 12 Aug 2010 10:51:16 -0400 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o7CEpC27026745 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 12 Aug 2010 09:51:15 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o7CEpBP1028891 for ; Thu, 12 Aug 2010 20:21:12 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Thu, 12 Aug 2010 20:21:11 +0530 From: "Premi, Sanjeev" To: "Menon, Nishanth" CC: "Gadiyar, Anand" , "linux-omap@vger.kernel.org" Date: Thu, 12 Aug 2010 20:21:11 +0530 Subject: RE: [PATCH] omap: Add macros to evaluate cpu revision Thread-Topic: [PATCH] omap: Add macros to evaluate cpu revision Thread-Index: Acspk4R045i+xe4BS1i7eLrYI6YxUwDQIr+wA1Xt2ZA= Message-ID: References: <1279725163-3481-1-git-send-email-premi@ti.com> <4C4710DB.6060901@ti.com> <5A47E75E594F054BAF48C5E4FC4B92AB0323B40084@dbde02.ent.ti.com> <4C481185.3090005@ti.com> <4C4821E9.6030405@ti.com> <4C482F8F.1090401@ti.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 12 Aug 2010 14:51:18 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 2e2ae53..36a7047 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -467,4 +469,103 @@ OMAP3_HAS_FEATURE(isp, ISP) OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) +/* + * Enumerate the CPU revisions for easy comparison against the + * revision bits specific for each processor family. + */ +#define DECLARE_CPU_REV(cpu) enum revs_ ##cpu +#define CPU_REV(cpu,rev,bits) cpu## _ ##rev = bits + +DECLARE_CPU_REV(omap242x) { + CPU_REV(omap242x, es1_0, 0x00), + CPU_REV(omap242x, es2_0, 0x01), +} ; + +DECLARE_CPU_REV(omap243x) { + CPU_REV(omap243x, es1_0, 0x00), +} ; + +DECLARE_CPU_REV(omap34xx) { + CPU_REV(omap34xx, es1_0, 0x00), + CPU_REV(omap34xx, es2_0, 0x01), + CPU_REV(omap34xx, es2_1, 0x02), + CPU_REV(omap34xx, es3_0, 0x03), + CPU_REV(omap34xx, es3_1, 0x04), + CPU_REV(omap34xx, es3_1_2, 0x05), +} ; + +DECLARE_CPU_REV(omap36xx) { + CPU_REV(omap36xx, es1_0, 0x00), + CPU_REV(omap36xx, es1_1, 0x01), +} ; + +DECLARE_CPU_REV(omap3503) { + CPU_REV(omap3503, es1_0, 0x00), + CPU_REV(omap3503, es2_0, 0x01), + CPU_REV(omap3503, es2_1, 0x02), + CPU_REV(omap3503, es3_0, 0x03), + CPU_REV(omap3503, es3_1, 0x04), +} ; + +DECLARE_CPU_REV(omap3515) { + CPU_REV(omap3515, es1_0, 0x00), + CPU_REV(omap3515, es2_0, 0x01), + CPU_REV(omap3515, es2_1, 0x02), + CPU_REV(omap3515, es3_0, 0x03), + CPU_REV(omap3515, es3_1, 0x04), +} ; + +DECLARE_CPU_REV(omap3525) { + CPU_REV(omap3525, es1_0, 0x00), + CPU_REV(omap3525, es2_0, 0x01), + CPU_REV(omap3525, es2_1, 0x02), + CPU_REV(omap3525, es3_0, 0x03), + CPU_REV(omap3525, es3_1, 0x04), +} ; + +DECLARE_CPU_REV(omap3530) { + CPU_REV(omap3530, es1_0, 0x00), + CPU_REV(omap3530, es2_0, 0x01), + CPU_REV(omap3530, es2_1, 0x02), + CPU_REV(omap3530, es3_0, 0x03), + CPU_REV(omap3530, es3_1, 0x04), +} ; + +DECLARE_CPU_REV(am3505) { + CPU_REV(am3505, es1_0, 0x00), + CPU_REV(am3505, es1_1, 0x01), +} ; + +DECLARE_CPU_REV(am3517) { + CPU_REV(am3517, es1_0, 0x00), + CPU_REV(am3517, es1_1, 0x01), +} ; + +/* + * Macros to evaluate CPU revision + */ +#define cpu_rev_lt(cpu,rev) \ + ((cpu_is_omap ##cpu() \ + && (GET_OMAP_REVISION() < cpu## _ ##rev)) ? 1 : 0) + +#define cpu_rev_le(cpu,rev) \ + ((cpu_is_omap ##cpu() \ + && (GET_OMAP_REVISION() <= cpu## _ ##rev)) ? 1 : 0) + +#define cpu_rev_eq(cpu,rev) \ + ((cpu_is_omap ##cpu() \ + && (GET_OMAP_REVISION() == cpu## _ ##rev)) ? 1 : 0) + +#define cpu_rev_ne(cpu,rev) \ + ((cpu_is_omap ##cpu() \ + && (GET_OMAP_REVISION() != cpu## _ ##rev)) ? 1 : 0) + +#define cpu_rev_ge(cpu,rev) \ + ((cpu_is_omap ##cpu() \ + && (GET_OMAP_REVISION() >= cpu## _ ##rev)) ? 1 : 0) + +#define cpu_rev_gt(cpu,rev) \ + ((cpu_is_omap ##cpu() \ + && (GET_OMAP_REVISION() > cpu## _ ##rev)) ? 1 : 0) + #endif