From patchwork Wed Jun 8 18:59:48 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 862192 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p58J0Ce2030591 for ; Wed, 8 Jun 2011 19:00:12 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753518Ab1FHTAK (ORCPT ); Wed, 8 Jun 2011 15:00:10 -0400 Received: from na3sys009aog115.obsmtp.com ([74.125.149.238]:42190 "EHLO na3sys009aog115.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753448Ab1FHTAJ convert rfc822-to-8bit (ORCPT ); Wed, 8 Jun 2011 15:00:09 -0400 Received: from mail-ww0-f49.google.com ([74.125.82.49]) (using TLSv1) by na3sys009aob115.postini.com ([74.125.148.12]) with SMTP ID DSNKTe/GuFGh48Ihrrzx5ITL/o1hagRuAO0b@postini.com; Wed, 08 Jun 2011 12:00:09 PDT Received: by mail-ww0-f49.google.com with SMTP id 39so665229wwb.18 for ; Wed, 08 Jun 2011 12:00:08 -0700 (PDT) Received: by 10.216.221.215 with SMTP id r65mr507630wep.73.1307559608071; Wed, 08 Jun 2011 12:00:08 -0700 (PDT) MIME-Version: 1.0 Received: by 10.216.2.66 with HTTP; Wed, 8 Jun 2011 11:59:48 -0700 (PDT) In-Reply-To: <87ei34i2ck.fsf@ti.com> References: <1307412330-25798-1-git-send-email-nm@ti.com> <1307412330-25798-4-git-send-email-nm@ti.com> <8762ohnwgb.fsf@ti.com> <87ei34i2ck.fsf@ti.com> From: "Menon, Nishanth" Date: Wed, 8 Jun 2011 13:59:48 -0500 Message-ID: Subject: Re: [pm-wip/cpufreq][PATCH 3/3] OMAP2+: cpufreq: do lateinit To: Kevin Hilman Cc: linux-omap Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Wed, 08 Jun 2011 19:00:12 +0000 (UTC) On Wed, Jun 8, 2011 at 13:51, Kevin Hilman wrote: [..] >> the issue is as follows: >> currently we dont do voltage transitions. when we do that >> eventually(and my current code has an forked implementation of dvfs, >> the following steps happen): >> late_initcall(omap2_common_pm_late_init); >> does pmic inits, omap_voltage_late_init, init_voltages and SR dev initialization >> >> without these, there is no way to transition MPU to proper voltage, >> frequency combination. The requirement will have to be that >> omap2-cpufreq.c allows for cpufreq transitions only after voltage and >> clk layers are ready for transitions - if we ever want to do dvfs - >> which we will eventually need to. > > Yes, I understand. > > But $SUBJECT patch is fixing this as an _init_ time ordering problem, > What you're describing is a runtime requirement that doesn't exist until > a DVFS transition is done.  IOW, the requirement is that the voltage > etc. layers have to be init'd before the first transition. > > So, rather than fix this with initcall ordering (which will have to be > redone as things git moved and converted to modules), just create a type > of late init function in this driver, which gets called on the first > transition. The tricky part ofcourse is for the registration - if we do the registration, omap_cpu_init will get called once the registration happens - no reason to stop it, which in turn triggers omap_target the moment the governors are ready to do their thing. Is the following what you are talking about? I am not completely sure how this helps.. Regards, Nishanth Menon --- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/mach-omap2/omap2plus-cpufreq.c b/arch/arm/mach-omap2/omap2plus-cpufreq.c index 77efcb0..8586df8 100644 --- a/arch/arm/mach-omap2/omap2plus-cpufreq.c +++ b/arch/arm/mach-omap2/omap2plus-cpufreq.c @@ -253,6 +253,11 @@ static struct cpufreq_driver omap_driver = { .attr = omap_cpufreq_attr, }; +static int __init omap_cpufreq_lateinit(void) +{ + return cpufreq_register_driver(&omap_driver); +} + static int __init omap_cpufreq_init(void) { if (cpu_is_omap24xx()) { @@ -277,8 +282,7 @@ static int __init omap_cpufreq_init(void) pr_warning("%s: unable to get the mpu device\n", __func__); return -EINVAL; } - - return cpufreq_register_driver(&omap_driver); + return 0; } static void __exit omap_cpufreq_exit(void) @@ -288,5 +292,6 @@ static void __exit omap_cpufreq_exit(void) MODULE_DESCRIPTION("cpufreq driver for OMAP2PLUS SOCs"); MODULE_LICENSE("GPL"); +late_initcall(omap_cpufreq_lateinit); module_init(omap_cpufreq_init); module_exit(omap_cpufreq_exit);