From patchwork Mon Jan 18 12:34:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "G.N, Vijayakumar" X-Patchwork-Id: 73652 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.2) with ESMTP id o0ICYpuK005885 for ; Mon, 18 Jan 2010 12:34:52 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754509Ab0ARMer (ORCPT ); Mon, 18 Jan 2010 07:34:47 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1754028Ab0ARMer (ORCPT ); Mon, 18 Jan 2010 07:34:47 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:41011 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752163Ab0ARMeq convert rfc822-to-8bit (ORCPT ); Mon, 18 Jan 2010 07:34:46 -0500 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id o0ICYgpX004609 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 18 Jan 2010 06:34:44 -0600 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id o0ICYgqR006287; Mon, 18 Jan 2010 18:04:42 +0530 (IST) Received: from dbde02.ent.ti.com ([172.24.170.145]) by dbde71.ent.ti.com ([172.24.170.149]) with mapi; Mon, 18 Jan 2010 18:04:42 +0530 From: "G.N, Vijayakumar" To: "linux-omap@vger.kernel.org" , "khilman@deeprootsystems.com" CC: "Sripathy, Vishwanath" , "Turquette, Mike" Date: Mon, 18 Jan 2010 18:04:24 +0530 Subject: [PATCHV2 1/2] OMAP3630: Clock: add clksel_shift to struct clk Thread-Topic: [PATCHV2 1/2] OMAP3630: Clock: add clksel_shift to struct clk Thread-Index: AcqYOm1PM1P90NSxTtyo0cA1SYPpgAAAAgpw Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index 6473247..ed17501 100755 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c @@ -537,6 +537,7 @@ static struct clk dpll3_m3_ck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL3_MASK, + .clksel_shift = OMAP3430_DIV_DPLL3_SHIFT, .clksel = div16_dpll3_clksel, .clkdm_name = "dpll3_clkdm", .recalc = &omap2_clksel_recalc, @@ -677,6 +678,7 @@ static struct clk dpll4_m2_ck_3630 __initdata = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), .clksel_mask = OMAP3630_DIV_96M_MASK, + .clksel_shift = OMAP3430_DIV_96M_SHIFT, .clksel = div32_dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, @@ -792,6 +794,7 @@ static struct clk dpll4_m3_ck_3630 __initdata = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3630_CLKSEL_TV_MASK, + .clksel_shift = OMAP3430_CLKSEL_TV_SHIFT, .clksel = div32_dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, @@ -892,6 +895,7 @@ static struct clk dpll4_m4_ck_3630 __initdata = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK, + .clksel_shift = OMAP3430_CLKSEL_DSS1_SHIFT, .clksel = div32_dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, @@ -933,6 +937,7 @@ static struct clk dpll4_m5_ck_3630 __initdata = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), .clksel_mask = OMAP3630_CLKSEL_CAM_MASK, + .clksel_shift = OMAP3430_CLKSEL_CAM_SHIFT, .clksel = div32_dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, @@ -970,6 +975,7 @@ static struct clk dpll4_m6_ck_3630 __initdata = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3630_DIV_DPLL4_MASK, + .clksel_shift = OMAP3430_DIV_DPLL4_SHIFT, .clksel = div32_dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 71d78f7..e841755 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -93,6 +93,7 @@ struct clk { #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ defined(CONFIG_ARCH_OMAP4) u8 fixed_div; + u8 clksel_shift; void __iomem *clksel_reg; u32 clksel_mask; const struct clksel *clksel;