From patchwork Thu Jan 2 15:07:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell King X-Patchwork-Id: 3425641 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BF492C02DC for ; Thu, 2 Jan 2014 15:16:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 46AC42015E for ; Thu, 2 Jan 2014 15:16:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D647220145 for ; Thu, 2 Jan 2014 15:16:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752158AbaABPPQ (ORCPT ); Thu, 2 Jan 2014 10:15:16 -0500 Received: from gw-1.arm.linux.org.uk ([78.32.30.217]:54169 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752136AbaABPPO (ORCPT ); Thu, 2 Jan 2014 10:15:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=arm.linux.org.uk; s=pandora; h=Date:Sender:Message-Id:Subject:Cc:To:From:References:In-Reply-To; bh=c8OJqy5n2Ps95vOmYUvT2eVKXVcer3VRWaVN6gyF7eg=; b=DhfMXeb5n1GcZI2VoEL2PkqAyYrR7eGXHr93Avywd+GwPvnVl9BQztZcvXW21YuA326oms/f+HHmlN+h41gNi1hpSwPpuItG7UDomKfQIE1ASjzbiG90Ful+0mi9iz6a8c65Tde1kzriontcBYw0N/ux8Tz89/KPjc3FgmHghck=; Received: from e0022681537dd.dyn.arm.linux.org.uk ([2002:4e20:1eda:1:222:68ff:fe15:37dd]:44113 helo=rmk-PC.arm.linux.org.uk) by pandora.arm.linux.org.uk with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.76) (envelope-from ) id 1Vyjrw-0003a0-OU; Thu, 02 Jan 2014 15:07:32 +0000 Received: from rmk by rmk-PC.arm.linux.org.uk with local (Exim 4.76) (envelope-from ) id 1Vyjrw-0004za-Cc; Thu, 02 Jan 2014 15:07:32 +0000 In-Reply-To: <20140102150621.GJ16456@n2100.arm.linux.org.uk> References: <20140102150621.GJ16456@n2100.arm.linux.org.uk> From: Russell King To: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead, org@arm.linux.org.uk, linux-omap@vger.kernel.org Cc: Vinod Koul , Dan Williams Subject: [PATCH RFC 04/26] dmaengine: omap-dma: consolidate writes to DMA registers Message-Id: Date: Thu, 02 Jan 2014 15:07:32 +0000 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There's no need to keep writing registers which don't change value in omap_dma_start_sg(). Move this into omap_dma_start_desc() and merge the register updates together. Signed-off-by: Russell King --- drivers/dma/omap-dma.c | 123 +++++++++++++++++++----------------------------- 1 files changed, 48 insertions(+), 75 deletions(-) diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c index dd233ca2cf5a..602c98aebca8 100644 --- a/drivers/dma/omap-dma.c +++ b/drivers/dma/omap-dma.c @@ -99,40 +99,75 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, unsigned idx) { struct omap_sg *sg = d->sg + idx; + + if (d->dir == DMA_DEV_TO_MEM) { + c->plat->dma_write(sg->addr, CDSA, c->dma_ch); + c->plat->dma_write(0, CDEI, c->dma_ch); + c->plat->dma_write(0, CDFI, c->dma_ch); + } else { + c->plat->dma_write(sg->addr, CSSA, c->dma_ch); + c->plat->dma_write(0, CSEI, c->dma_ch); + c->plat->dma_write(0, CSFI, c->dma_ch); + } + + c->plat->dma_write(sg->en, CEN, c->dma_ch); + c->plat->dma_write(sg->fn, CFN, c->dma_ch); + + omap_start_dma(c->dma_ch); +} + +static void omap_dma_start_desc(struct omap_chan *c) +{ + struct virt_dma_desc *vd = vchan_next_desc(&c->vc); + struct omap_desc *d; uint32_t val; + if (!vd) { + c->desc = NULL; + return; + } + + list_del(&vd->node); + + c->desc = d = to_omap_dma_desc(&vd->tx); + c->sgidx = 0; + if (d->dir == DMA_DEV_TO_MEM) { if (dma_omap1()) { val = c->plat->dma_read(CSDP, c->dma_ch); - val &= ~(0x1f << 9); + val &= ~(0x1f << 9 | 0x1f << 2); val |= OMAP_DMA_PORT_EMIFF << 9; + val |= d->periph_port << 2; c->plat->dma_write(val, CSDP, c->dma_ch); } val = c->plat->dma_read(CCR, c->dma_ch); - val &= ~(0x03 << 14); + val &= ~(0x03 << 14 | 0x03 << 12); val |= OMAP_DMA_AMODE_POST_INC << 14; + val |= OMAP_DMA_AMODE_CONSTANT << 12; c->plat->dma_write(val, CCR, c->dma_ch); - c->plat->dma_write(sg->addr, CDSA, c->dma_ch); - c->plat->dma_write(0, CDEI, c->dma_ch); - c->plat->dma_write(0, CDFI, c->dma_ch); + c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch); + c->plat->dma_write(0, CSEI, c->dma_ch); + c->plat->dma_write(d->fi, CSFI, c->dma_ch); } else { if (dma_omap1()) { val = c->plat->dma_read(CSDP, c->dma_ch); - val &= ~(0x1f << 2); + val &= ~(0x1f << 9 | 0x1f << 2); + val |= d->periph_port << 9; val |= OMAP_DMA_PORT_EMIFF << 2; c->plat->dma_write(val, CSDP, c->dma_ch); } val = c->plat->dma_read(CCR, c->dma_ch); - val &= ~(0x03 << 12); + val &= ~(0x03 << 12 | 0x03 << 14); + val |= OMAP_DMA_AMODE_CONSTANT << 14; val |= OMAP_DMA_AMODE_POST_INC << 12; c->plat->dma_write(val, CCR, c->dma_ch); - c->plat->dma_write(sg->addr, CSSA, c->dma_ch); - c->plat->dma_write(0, CSEI, c->dma_ch); - c->plat->dma_write(0, CSFI, c->dma_ch); + c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch); + c->plat->dma_write(0, CDEI, c->dma_ch); + c->plat->dma_write(d->fi, CDFI, c->dma_ch); } val = c->plat->dma_read(CSDP, c->dma_ch); @@ -158,91 +193,29 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, val = c->plat->dma_read(CCR, c->dma_ch); /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ - val &= ~((1 << 23) | (3 << 19) | 0x1f); + val &= ~(1 << 24 | 1 << 23 | 3 << 19 | 1 << 18 | 1 << 5 | 0x1f); val |= (c->dma_sig & ~0x1f) << 14; val |= c->dma_sig & 0x1f; if (d->sync_mode & OMAP_DMA_SYNC_FRAME) val |= 1 << 5; - else - val &= ~(1 << 5); if (d->sync_mode & OMAP_DMA_SYNC_BLOCK) val |= 1 << 18; - else - val &= ~(1 << 18); switch (d->sync_type) { - case OMAP_DMA_DST_SYNC_PREFETCH: - val &= ~(1 << 24); /* dest synch */ + case OMAP_DMA_DST_SYNC_PREFETCH:/* dest synch */ val |= 1 << 23; /* Prefetch */ break; case 0: - val &= ~(1 << 24); /* dest synch */ break; default: - val |= 1 << 24; /* source synch */ + val |= 1 << 24; /* source synch */ break; } c->plat->dma_write(val, CCR, c->dma_ch); } - c->plat->dma_write(sg->en, CEN, c->dma_ch); - c->plat->dma_write(sg->fn, CFN, c->dma_ch); - - omap_start_dma(c->dma_ch); -} - -static void omap_dma_start_desc(struct omap_chan *c) -{ - struct virt_dma_desc *vd = vchan_next_desc(&c->vc); - struct omap_desc *d; - uint32_t val; - - if (!vd) { - c->desc = NULL; - return; - } - - list_del(&vd->node); - - c->desc = d = to_omap_dma_desc(&vd->tx); - c->sgidx = 0; - - if (d->dir == DMA_DEV_TO_MEM) { - if (dma_omap1()) { - val = c->plat->dma_read(CSDP, c->dma_ch); - val &= ~(0x1f << 2); - val |= d->periph_port << 2; - c->plat->dma_write(val, CSDP, c->dma_ch); - } - - val = c->plat->dma_read(CCR, c->dma_ch); - val &= ~(0x03 << 12); - val |= OMAP_DMA_AMODE_CONSTANT << 12; - c->plat->dma_write(val, CCR, c->dma_ch); - - c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch); - c->plat->dma_write(0, CSEI, c->dma_ch); - c->plat->dma_write(d->fi, CSFI, c->dma_ch); - } else { - if (dma_omap1()) { - val = c->plat->dma_read(CSDP, c->dma_ch); - val &= ~(0x1f << 9); - val |= d->periph_port << 9; - c->plat->dma_write(val, CSDP, c->dma_ch); - } - - val = c->plat->dma_read(CCR, c->dma_ch); - val &= ~(0x03 << 14); - val |= OMAP_DMA_AMODE_CONSTANT << 14; - c->plat->dma_write(val, CCR, c->dma_ch); - - c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch); - c->plat->dma_write(0, CDEI, c->dma_ch); - c->plat->dma_write(d->fi, CDFI, c->dma_ch); - } - omap_dma_start_sg(c, d, 0); }