diff mbox

[RFC,v2,3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations

Message ID Pine.LNX.4.64.1212131522430.18586@axis700.grange (mailing list archive)
State New, archived
Headers show

Commit Message

Guennadi Liakhovetski Dec. 13, 2012, 2:32 p.m. UTC
On Thu, 13 Dec 2012, Will Deacon wrote:

> On Thu, Dec 13, 2012 at 08:09:33AM +0000, Guennadi Liakhovetski wrote:
> > On Wed, 12 Dec 2012, Will Deacon wrote:
> > > Back to the case in hand.... Lorenzo just pointed out to me that the
> > > finished in question (sh7372_do_idle_sysc) calls v7_flush_dcache_all, so
> > > the louis stuff should be irrelevant. The problem may actually be that the
> > > finisher disables the L2 cache prior to cleaning/invalidating it, which is
> > > the opposite order to that described by the A8 TRM.
> > > 
> > > Guennadi -- can you try moving the kernel_flush call before the L2 disable
> > > in sh7372_do_idle_sysc please?
> > 
> > Yes, this works too.
> 
> That's good to know. Please can you send a patch for that? The sequence
> currently being used by the finisher *is* buggy, and should be fixed
> independently of the louis stuff.

Well, the fix is yours, so, it should be "From: you." I can certainly send 
it just copying your description above, but I'd also need your Sob. 
Something like the below (feel free to improve the subject line and the 
description):

From: Will Deacon <will.deacon@arm.com>
Subject: [PATCH] ARM: sh7372: fix cache clean / invalidate order

According to the Cortex A8 TRM the L2 cache should be first cleaned and 
then disabled. Fix the swapped order on sh7372.

Signed-off-by: <you>
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
(or even just)
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>

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Comments

Santosh Shilimkar Dec. 13, 2012, 2:39 p.m. UTC | #1
On Thursday 13 December 2012 03:32 PM, Guennadi Liakhovetski wrote:
> On Thu, 13 Dec 2012, Will Deacon wrote:
>
>> On Thu, Dec 13, 2012 at 08:09:33AM +0000, Guennadi Liakhovetski wrote:
>>> On Wed, 12 Dec 2012, Will Deacon wrote:
>>>> Back to the case in hand.... Lorenzo just pointed out to me that the
>>>> finished in question (sh7372_do_idle_sysc) calls v7_flush_dcache_all, so
>>>> the louis stuff should be irrelevant. The problem may actually be that the
>>>> finisher disables the L2 cache prior to cleaning/invalidating it, which is
>>>> the opposite order to that described by the A8 TRM.
>>>>
>>>> Guennadi -- can you try moving the kernel_flush call before the L2 disable
>>>> in sh7372_do_idle_sysc please?
>>>
>>> Yes, this works too.
>>
>> That's good to know. Please can you send a patch for that? The sequence
>> currently being used by the finisher *is* buggy, and should be fixed
>> independently of the louis stuff.
>
> Well, the fix is yours, so, it should be "From: you." I can certainly send
> it just copying your description above, but I'd also need your Sob.
> Something like the below (feel free to improve the subject line and the
> description):
>
> From: Will Deacon <will.deacon@arm.com>
> Subject: [PATCH] ARM: sh7372: fix cache clean / invalidate order
>
> According to the Cortex A8 TRM the L2 cache should be first cleaned and
> then disabled. Fix the swapped order on sh7372.
>
> Signed-off-by: <you>
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
> (or even just)
> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
>
> diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
> index 1d56467..df15d8a 100644
> --- a/arch/arm/mach-shmobile/sleep-sh7372.S
> +++ b/arch/arm/mach-shmobile/sleep-sh7372.S
> @@ -59,16 +59,16 @@ sh7372_do_idle_sysc:
>   	mcr	p15, 0, r0, c1, c0, 0
>   	isb
>
> -	/* disable L2 cache in the aux control register */
> -	mrc     p15, 0, r10, c1, c0, 1
> -	bic     r10, r10, #2
> -	mcr     p15, 0, r10, c1, c0, 1
> -
>   	/*
>   	 * Invalidate data cache again.
>   	 */
kernel_flush does "Clean and Invalidate"
>   	ldr	r1, kernel_flush
>   	blx	r1
> +
> +	/* disable L2 cache in the aux control register */
> +	mrc     p15, 0, r10, c1, c0, 1
> +	bic     r10, r10, #2
> +	mcr     p15, 0, r10, c1, c0, 1
An isb will be make it safe.

Otherwise patch looks good to me.
Feel free to add my review-by tag if you need one.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>


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Will Deacon Dec. 13, 2012, 2:52 p.m. UTC | #2
On Thu, Dec 13, 2012 at 02:32:46PM +0000, Guennadi Liakhovetski wrote:
> On Thu, 13 Dec 2012, Will Deacon wrote:
> 
> > On Thu, Dec 13, 2012 at 08:09:33AM +0000, Guennadi Liakhovetski wrote:
> > > On Wed, 12 Dec 2012, Will Deacon wrote:
> > > > Back to the case in hand.... Lorenzo just pointed out to me that the
> > > > finished in question (sh7372_do_idle_sysc) calls v7_flush_dcache_all, so
> > > > the louis stuff should be irrelevant. The problem may actually be that the
> > > > finisher disables the L2 cache prior to cleaning/invalidating it, which is
> > > > the opposite order to that described by the A8 TRM.
> > > > 
> > > > Guennadi -- can you try moving the kernel_flush call before the L2 disable
> > > > in sh7372_do_idle_sysc please?
> > > 
> > > Yes, this works too.
> > 
> > That's good to know. Please can you send a patch for that? The sequence
> > currently being used by the finisher *is* buggy, and should be fixed
> > independently of the louis stuff.
> 
> Well, the fix is yours, so, it should be "From: you." I can certainly send 
> it just copying your description above, but I'd also need your Sob. 
> Something like the below (feel free to improve the subject line and the 
> description):

No, I didn't send any code for this so you should be the author. I can
review/possibly ack it if you like (please send a v2 addressing Santosh's
comments).

Will
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diff mbox

Patch

diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index 1d56467..df15d8a 100644
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -59,16 +59,16 @@  sh7372_do_idle_sysc:
 	mcr	p15, 0, r0, c1, c0, 0
 	isb
 
-	/* disable L2 cache in the aux control register */
-	mrc     p15, 0, r10, c1, c0, 1
-	bic     r10, r10, #2
-	mcr     p15, 0, r10, c1, c0, 1
-
 	/*
 	 * Invalidate data cache again.
 	 */
 	ldr	r1, kernel_flush
 	blx	r1
+
+	/* disable L2 cache in the aux control register */
+	mrc     p15, 0, r10, c1, c0, 1
+	bic     r10, r10, #2
+	mcr     p15, 0, r10, c1, c0, 1
 	/*
 	 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
 	 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.