| Message ID | 1402070140-15090-3-git-send-email-davidlohr@hp.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
On Fri, 2014-06-06 at 08:55 -0700, Davidlohr Bueso wrote: > PA-RISC's cmpxchg is not save against normal stores and the code used > for optimistic spinning is known broken because of this. What about all the other identified architectures? The problem is that unless you can do an atomic Read Modify Write on your architecture, you have to implement our exchange primitives with locking, and that makes you unsafe against stores We happen to be the architecture that detected this, but I thought we agreed sparc32, metag, tile32, arc and possibly hexagon have this problem. Rather than naming all the failing architectures, we probably want an ARCH_NO_ATOMIC_RMW symbol which they select to indicate they can't do atomic exchange and then you make depends on SMP && RWSEM_XCHGADD_ALGORITHM &!ARCH_NO_ATOMIC_RMW So they can all self select (especially if more come crawling out of the woodwork). James -- To unsubscribe from this list: send the line "unsubscribe linux-parisc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/kernel/Kconfig.locks b/kernel/Kconfig.locks index e4c3162..125c77a 100644 --- a/kernel/Kconfig.locks +++ b/kernel/Kconfig.locks @@ -226,7 +226,7 @@ config MUTEX_SPIN_ON_OWNER config RWSEM_SPIN_ON_OWNER def_bool y - depends on SMP && RWSEM_XCHGADD_ALGORITHM + depends on SMP && RWSEM_XCHGADD_ALGORITHM && !PARISC config ARCH_USE_QUEUE_RWLOCK bool
PA-RISC's cmpxchg is not save against normal stores and the code used for optimistic spinning is known broken because of this. Disable for now. [Changelog from PeterZ] Reported-by: Mikulas Patocka <mpatocka@redhat.com> Signed-off-by: Davidlohr Bueso <davidlohr@hp.com> --- kernel/Kconfig.locks | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)