diff mbox

parisc: Fix TLB related boot crash with PA8000-PA8700 CPUs

Message ID 20161207205240.GA5917@ls3530 (mailing list archive)
State Superseded
Headers show

Commit Message

Helge Deller Dec. 7, 2016, 8:52 p.m. UTC
Machines with PA8000-PA8700 CPUs crash during startup while we measure
and calculate a good threshold for the TLB flush.

Avoid this crash by simply skipping the test until we figure out what
really triggers the crash.

Cc: <stable@vger.kernel.org> # v3.18+
Signed-off-by: Helge Deller <deller@gmx.de>

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Comments

Aaro Koskinen Dec. 7, 2016, 9:34 p.m. UTC | #1
On Wed, Dec 07, 2016 at 09:52:40PM +0100, Helge Deller wrote:
> Machines with PA8000-PA8700 CPUs crash during startup while we measure
> and calculate a good threshold for the TLB flush.

I haven't seen any crashed on HP c3700 (PA8700)...

A.
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John David Anglin Dec. 7, 2016, 10:17 p.m. UTC | #2
On 2016-12-07 4:34 PM, Aaro Koskinen wrote:
> On Wed, Dec 07, 2016 at 09:52:40PM +0100, Helge Deller wrote:
>> Machines with PA8000-PA8700 CPUs crash during startup while we measure
>> and calculate a good threshold for the TLB flush.
> I haven't seen any crashed on HP c3700 (PA8700)...
I believe the issue only affects SMP machines.  My c3750 also boots okay.

Dave
Helge Deller Dec. 8, 2016, 7:58 p.m. UTC | #3
Hi Aaro,

On 07.12.2016 22:34, Aaro Koskinen wrote:
> On Wed, Dec 07, 2016 at 09:52:40PM +0100, Helge Deller wrote:
>> Machines with PA8000-PA8700 CPUs crash during startup while we measure
>> and calculate a good threshold for the TLB flush.
> 
> I haven't seen any crashed on HP c3700 (PA8700)...

Thanks for the feedback!
I did some additional analysis today, and it happens only on SMP machines.
I could reproduce the crash on a A500-44 and a J5000, both are 2-way boxes.

Helge
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diff mbox

Patch

diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index c263301..63c10ea 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -393,6 +393,14 @@  void __init parisc_setup_cache_timing(void)
 
 	/* calculate TLB flush threshold */
 
+	/* skip TLB measure on PA8000-PA8700 CPUs */
+	if (boot_cpu_data.cpu_type >= pcxu &&
+	    boot_cpu_data.cpu_type <= pcxw2) {
+		threshold = max(cache_info.it_size, cache_info.dt_size);
+		threshold *= PAGE_SIZE;
+		goto set_tlb_threshold;
+	}
+
 	alltime = mfctl(16);
 	flush_tlb_all();
 	alltime = mfctl(16) - alltime;
@@ -411,6 +419,8 @@  void __init parisc_setup_cache_timing(void)
 		alltime, size, rangetime);
 
 	threshold = PAGE_ALIGN(num_online_cpus() * size * alltime / rangetime);
+
+set_tlb_threshold:
 	if (threshold)
 		parisc_tlb_flush_threshold = threshold;
 	printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",