From patchwork Sat Oct 27 22:03:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 10658463 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A33421734 for ; Sat, 27 Oct 2018 22:03:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 81785283A2 for ; Sat, 27 Oct 2018 22:03:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5BF5828403; Sat, 27 Oct 2018 22:03:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C1FC5283A2 for ; Sat, 27 Oct 2018 22:03:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728185AbeJ1Gpv (ORCPT ); Sun, 28 Oct 2018 02:45:51 -0400 Received: from simcoe207srvr.owm.bell.net ([184.150.200.207]:57583 "EHLO torfep01.bell.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726625AbeJ1Gpv (ORCPT ); Sun, 28 Oct 2018 02:45:51 -0400 Received: from bell.net torfep01 184.150.200.158 by torfep01.bell.net with ESMTP id <20181027220327.TZOC31136.torfep01.bell.net@torspm01.bell.net> for ; Sat, 27 Oct 2018 18:03:27 -0400 Received: from mx3210.localdomain ([70.53.62.196]) by torspm01.bell.net with ESMTP id <20181027220327.YHHA10318.torspm01.bell.net@mx3210.localdomain>; Sat, 27 Oct 2018 18:03:27 -0400 Received: by mx3210.localdomain (Postfix, from userid 1000) id 430562200ED; Sat, 27 Oct 2018 18:03:26 -0400 (EDT) Date: Sat, 27 Oct 2018 18:03:25 -0400 From: John David Anglin To: linux-parisc Cc: Helge Deller , James Bottomley , Meelis Roos Subject: [PATCH] parisc: Maybe fix A500 boot crash with 44786880df196a4200c178945c4d41675faf9fb7 Message-ID: <20181027220324.GA24329@mx3210.localdomain> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) X-Cloudmark-Analysis: v=2.2 cv=N5jGLy1B c=1 sm=0 tr=0 a=Zvhif4XNTjWcJyJCfFIh1A==:17 a=7rEXaN4VY4IA:10 a=smKx5t2vBNcA:10 a=FBHGMhGWAAAA:8 a=BkLKKtRArlrcwQkgDokA:9 a=CjuIK1q_8ugA:10 a=RnQ-AL6LzFKGfa6aekYA:9 a=ONNS8QRKHyMA:10 a=9gvnlMMaQFpL9xblJ6ne:22 Sender: linux-parisc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-parisc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP I believe the following change will fix the cache/TLB inconsistency observed by Meelis. After changing the page table entries, we need to flush the cache and TLB to ensure that we don't have any stale PTE values in the cache or TLB. The alternative patching is done after all CPUs are running. Thus, we need to flush the whole cache and TLB. I included the init section in the range modified by map_pages as suggested by Helge. Some routines in the init section may require patching. Signed-off-by: John David Anglin diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c index e7e626bcd0be..f88a52b8531c 100644 --- a/arch/parisc/mm/init.c +++ b/arch/parisc/mm/init.c @@ -513,17 +513,15 @@ static void __init map_pages(unsigned long start_vaddr, void __init set_kernel_text_rw(int enable_read_write) { - unsigned long start = (unsigned long)_stext; + unsigned long start = (unsigned long)__init_begin; unsigned long end = (unsigned long)_etext; map_pages(start, __pa(start), end-start, PAGE_KERNEL_RWX, enable_read_write ? 1:0); - /* force the kernel to see the new TLB entries */ - __flush_tlb_range(0, start, end); - - /* dump old cached instructions */ - flush_icache_range(start, end); + /* force the kernel to see the new page table entries */ + flush_cache_all(); + flush_tlb_all(); } void __ref free_initmem(void)