diff mbox series

[4/4] parisc/unaligned: Tweak 32-bit inline assembly of emulate_sth()

Message ID 20220223165455.3764-4-deller@gmx.de (mailing list archive)
State Accepted, archived
Headers show
Series [1/4] parisc/unaligned: Tweak inline assembly of emulate_ldh() | expand

Commit Message

Helge Deller Feb. 23, 2022, 4:54 p.m. UTC 
Convert to use real temp variables instead of clobbering processor
registers.

Signed-off-by: Helge Deller <deller@gmx.de>
---
 arch/parisc/kernel/unaligned.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

--
2.34.1
diff mbox series

Patch

diff --git a/arch/parisc/kernel/unaligned.c b/arch/parisc/kernel/unaligned.c
index 8fbe000b33e7..0d6e90d6f497 100644
--- a/arch/parisc/kernel/unaligned.c
+++ b/arch/parisc/kernel/unaligned.c
@@ -234,7 +234,7 @@  static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)

 static int emulate_sth(struct pt_regs *regs, int frreg)
 {
-	unsigned long val = regs->gr[frreg];
+	unsigned long val = regs->gr[frreg], temp1;
 	ASM_EXCEPTIONTABLE_VAR(ret);

 	if (!frreg)
@@ -244,16 +244,15 @@  static int emulate_sth(struct pt_regs *regs, int frreg)
 		val, regs->isr, regs->ior);

 	__asm__ __volatile__ (
-"	mtsp %3, %%sr1\n"
-"	extrw,u %1, 23, 8, %%r19\n"
-"1:	stb %1, 1(%%sr1, %2)\n"
-"2:	stb %%r19, 0(%%sr1, %2)\n"
+"	mtsp %4, %%sr1\n"
+"	extrw,u %2, 23, 8, %1\n"
+"1:	stb %1, 0(%%sr1, %3)\n"
+"2:	stb %2, 1(%%sr1, %3)\n"
 "3:	\n"
 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
 	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
-	: "+r" (ret)
-	: "r" (val), "r" (regs->ior), "r" (regs->isr)
-	: "r19" );
+	: "+r" (ret), "=&r" (temp1)
+	: "r" (val), "r" (regs->ior), "r" (regs->isr) );

 	return ret;
 }