diff mbox

parisc: fix LMMIO mismatch between PAT length and MASK register

Message ID BLU0-SMTP393134EC9554B3C1E34F9297790@phx.gbl (mailing list archive)
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John David Anglin July 9, 2013, 11:35 p.m. UTC 
On 9-Jul-13, at 4:59 PM, John David Anglin wrote:

> On 7/9/2013 3:45 PM, Alex Ivanov wrote:
>> The panic on SMP kernel changed to another one:
>> http://pastebin.com/SfUfd0Un
> This is just a guess but I don't think page is valid
> if the pfn is not valid.  You might try this untested change.
>
> flush_cache_mm might have same problem (i.e., we may need to
> check whether the pfn for the pte is valid).

This version compiles and boots on rp3440.

Dave
--
John David Anglin	dave.anglin@bell.net

Comments

Alex Ivanov July 10, 2013, 8:19 p.m. UTC | #1 
Sorry for not CC'ing to the list.

10.07.2013, 03:35, "John David Anglin" <dave.anglin@bell.net>:

>  On 9-Jul-13, at 4:59 PM, John David Anglin wrote:
>>   On 7/9/2013 3:45 PM, Alex Ivanov wrote:
>>>   The panic on SMP kernel changed to another one:
>>>   http://pastebin.com/SfUfd0Un
>>   This is just a guess but I don't think page is valid
>>   if the pfn is not valid.  You might try this untested change.
>>
>>   flush_cache_mm might have same problem (i.e., we may need to
>>   check whether the pfn for the pte is valid).
>  This version compiles and boots on rp3440.
>
>  Dave
>  --
>  John David Anglin dave.anglin@bell.net

Dave,

Thank you so much! Your guess looks to be right. After applying of your
patch there was no more KP and X just worked.
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John David Anglin July 10, 2013, 8:28 p.m. UTC | #2 
On 7/10/2013 4:19 PM, Alex Ivanov wrote:
> Sorry for not CC'ing to the list.
>
> 10.07.2013, 03:35, "John David Anglin" <dave.anglin@bell.net>:
>
>>   On 9-Jul-13, at 4:59 PM, John David Anglin wrote:
>>>    On 7/9/2013 3:45 PM, Alex Ivanov wrote:
>>>>    The panic on SMP kernel changed to another one:
>>>>    http://pastebin.com/SfUfd0Un
>>>    This is just a guess but I don't think page is valid
>>>    if the pfn is not valid.  You might try this untested change.
>>>
>>>    flush_cache_mm might have same problem (i.e., we may need to
>>>    check whether the pfn for the pte is valid).
>>   This version compiles and boots on rp3440.
>>
>>   Dave
>>   --
>>   John David Anglin dave.anglin@bell.net
> Dave,
>
> Thank you so much! Your guess looks to be right. After applying of your
> patch there was no more KP and X just worked.
I have been studying this issue a bit more.  It looks to me as if it 
would be better to call
vm_normal_page to get the page.  It returns NULL when we a have special 
mapping that
doesn't want to be associated with a struct page.  See comment in 
mm/memory.c.

I'll send a patch when I get a chance to test this approach.

Dave
Matt Turner July 10, 2013, 9:14 p.m. UTC | #3 
On Wed, Jul 10, 2013 at 1:19 PM, Alex Ivanov <gnidorah@p0n4ik.tk> wrote:
> Thank you so much! Your guess looks to be right. After applying of your
> patch there was no more KP and X just worked.

Nice! Does DRI work?
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Alex Ivanov July 10, 2013, 9:29 p.m. UTC | #4 
11.07.2013, 01:14, "Matt Turner" <mattst88@gmail.com>:
> On Wed, Jul 10, 2013 at 1:19 PM, Alex Ivanov <gnidorah@p0n4ik.tk> wrote:
>
>>  Thank you so much! Your guess looks to be right. After applying of your
>>  patch there was no more KP and X just worked.
>
> Nice! Does DRI work?

Not on my side. Plus i can't visually jump over 8bit depth, although Xorg 
states 24bit in it's log.
As for DRI, i'm experiencing 
"ring test failed (scratch(0x15E4)=0xCAFEDEAD)" with a firegl x3.

Can't figure out why, the ring vaddr (0x0000000060001000) is within the
limits of dma32. But the ring test fails. And i'm afraid that just adding a 
buffer bounces in places will not help.
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Helge Deller July 11, 2013, 7:47 p.m. UTC | #5 
adding linux parisc mailing list...:

On 07/11/2013 09:46 PM, Helge Deller wrote:
> On 07/10/2013 11:29 PM, Alex Ivanov wrote:
>> 11.07.2013, 01:14, "Matt Turner" <mattst88@gmail.com>:
>>> On Wed, Jul 10, 2013 at 1:19 PM, Alex Ivanov <gnidorah@p0n4ik.tk> wrote:
>>>
>>>>  Thank you so much! Your guess looks to be right. After applying of your
>>>>  patch there was no more KP and X just worked.
>>>
>>> Nice! Does DRI work?
>>
>> Not on my side. Plus i can't visually jump over 8bit depth, although Xorg 
>> states 24bit in it's log.
>> As for DRI, i'm experiencing 
>> "ring test failed (scratch(0x15E4)=0xCAFEDEAD)" with a firegl x3.
> 
> FWIW, I'm seeing the same failure on my FireGL X1:
> 80:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI Radeon R300 NG [FireGL X1] (rev 80)
> 
> [drm] radeon: irq initialized.
> [drm] Loading R300 Microcode
> [drm] radeon: ring at 0x0000000060001000
> [drm:r100_ring_test] *ERROR* radeon: ring test failed (scratch(0x15E4)=0xCAFEDEAD)
> [drm:r100_cp_init] *ERROR* radeon: cp isn't working (-22).
> radeon 0000:80:00.0: failed initializing CP (-22).
> radeon 0000:80:00.0: Disabling GPU acceleration
> [drm:r100_cp_fini] *ERROR* Wait for CP idle timeout, shutting down CP.
> [drm] radeon: cp finalized
> [drm] radeon: cp finalized
> 
> I haven't tested X11 yet.
> 
>> Can't figure out why, the ring vaddr (0x0000000060001000) is within the
>> limits of dma32. But the ring test fails. And i'm afraid that just adding a 
>> buffer bounces in places will not help.
> 
> Helge
> 

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Alex Ivanov Aug. 4, 2013, 11 a.m. UTC | #6 
11.07.2013, 23:48, "Helge Deller" <deller@gmx.de>:
> adding linux parisc mailing list...:
>
> On 07/11/2013 09:46 PM, Helge Deller wrote:
>
>>  On 07/10/2013 11:29 PM, Alex Ivanov wrote:
>>>  11.07.2013, 01:14, "Matt Turner" <mattst88@gmail.com>:
>>>>  On Wed, Jul 10, 2013 at 1:19 PM, Alex Ivanov <gnidorah@p0n4ik.tk> wrote:
>>>>>   Thank you so much! Your guess looks to be right. After applying of your
>>>>>   patch there was no more KP and X just worked.
>>>>  Nice! Does DRI work?
>>>  Not on my side. Plus i can't visually jump over 8bit depth, although Xorg
>>>  states 24bit in it's log.
>>>  As for DRI, i'm experiencing
>>>  "ring test failed (scratch(0x15E4)=0xCAFEDEAD)" with a firegl x3.
>>  FWIW, I'm seeing the same failure on my FireGL X1:
>>  80:00.0 VGA compatible controller: Advanced Micro Devices [AMD] nee ATI Radeon R300 NG [FireGL X1] (rev 80)
>>
>>  [drm] radeon: irq initialized.
>>  [drm] Loading R300 Microcode
>>  [drm] radeon: ring at 0x0000000060001000
>>  [drm:r100_ring_test] *ERROR* radeon: ring test failed (scratch(0x15E4)=0xCAFEDEAD)
>>  [drm:r100_cp_init] *ERROR* radeon: cp isn't working (-22).
>>  radeon 0000:80:00.0: failed initializing CP (-22).
>>  radeon 0000:80:00.0: Disabling GPU acceleration
>>  [drm:r100_cp_fini] *ERROR* Wait for CP idle timeout, shutting down CP.
>>  [drm] radeon: cp finalized
>>  [drm] radeon: cp finalized

I still have no clue why this happens. Broken SBA IOMMU / DRM code? Missing syncing primitives?
Should we forward this to dri-devel mail list?
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John David Anglin Aug. 4, 2013, 3:44 p.m. UTC | #7 
On 4-Aug-13, at 7:00 AM, Alex Ivanov wrote:

> 11.07.2013, 23:48, "Helge Deller" <deller@gmx.de>:
>> adding linux parisc mailing list...:
>>
>> On 07/11/2013 09:46 PM, Helge Deller wrote:
>>
>>>  On 07/10/2013 11:29 PM, Alex Ivanov wrote:
>>>>  11.07.2013, 01:14, "Matt Turner" <mattst88@gmail.com>:
>>>>>  On Wed, Jul 10, 2013 at 1:19 PM, Alex Ivanov  
>>>>> <gnidorah@p0n4ik.tk> wrote:
>>>>>>   Thank you so much! Your guess looks to be right. After  
>>>>>> applying of your
>>>>>>   patch there was no more KP and X just worked.
>>>>>  Nice! Does DRI work?
>>>>  Not on my side. Plus i can't visually jump over 8bit depth,  
>>>> although Xorg
>>>>  states 24bit in it's log.
>>>>  As for DRI, i'm experiencing
>>>>  "ring test failed (scratch(0x15E4)=0xCAFEDEAD)" with a firegl x3.
>>>  FWIW, I'm seeing the same failure on my FireGL X1:
>>>  80:00.0 VGA compatible controller: Advanced Micro Devices [AMD]  
>>> nee ATI Radeon R300 NG [FireGL X1] (rev 80)
>>>
>>>  [drm] radeon: irq initialized.
>>>  [drm] Loading R300 Microcode
>>>  [drm] radeon: ring at 0x0000000060001000
>>>  [drm:r100_ring_test] *ERROR* radeon: ring test failed  
>>> (scratch(0x15E4)=0xCAFEDEAD)
>>>  [drm:r100_cp_init] *ERROR* radeon: cp isn't working (-22).
>>>  radeon 0000:80:00.0: failed initializing CP (-22).
>>>  radeon 0000:80:00.0: Disabling GPU acceleration
>>>  [drm:r100_cp_fini] *ERROR* Wait for CP idle timeout, shutting  
>>> down CP.
>>>  [drm] radeon: cp finalized
>>>  [drm] radeon: cp finalized
>
> I still have no clue why this happens. Broken SBA IOMMU / DRM code?  
> Missing syncing primitives?

I wonder if there is a endian issue in the microcode load.

Dave
--
John David Anglin	dave.anglin@bell.net



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Matt Turner Aug. 4, 2013, 4:28 p.m. UTC | #8 
On Sun, Aug 4, 2013 at 8:44 AM, John David Anglin <dave.anglin@bell.net> wrote:
> I wonder if there is a endian issue in the microcode load.

It should work on PowerPC (big-endian).
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John David Anglin Aug. 10, 2013, 7:41 p.m. UTC | #9 
On 4-Aug-13, at 7:00 AM, Alex Ivanov wrote:

> 11.07.2013, 23:48, "Helge Deller" <deller@gmx.de>:
>> adding linux parisc mailing list...:
>>
>> On 07/11/2013 09:46 PM, Helge Deller wrote:
>>
>>>  On 07/10/2013 11:29 PM, Alex Ivanov wrote:
>>>>  11.07.2013, 01:14, "Matt Turner" <mattst88@gmail.com>:
>>>>>  On Wed, Jul 10, 2013 at 1:19 PM, Alex Ivanov  
>>>>> <gnidorah@p0n4ik.tk> wrote:
>>>>>>   Thank you so much! Your guess looks to be right. After  
>>>>>> applying of your
>>>>>>   patch there was no more KP and X just worked.
>>>>>  Nice! Does DRI work?
>>>>  Not on my side. Plus i can't visually jump over 8bit depth,  
>>>> although Xorg
>>>>  states 24bit in it's log.
>>>>  As for DRI, i'm experiencing
>>>>  "ring test failed (scratch(0x15E4)=0xCAFEDEAD)" with a firegl x3.
>>>  FWIW, I'm seeing the same failure on my FireGL X1:
>>>  80:00.0 VGA compatible controller: Advanced Micro Devices [AMD]  
>>> nee ATI Radeon R300 NG [FireGL X1] (rev 80)
>>>
>>>  [drm] radeon: irq initialized.
>>>  [drm] Loading R300 Microcode
>>>  [drm] radeon: ring at 0x0000000060001000
>>>  [drm:r100_ring_test] *ERROR* radeon: ring test failed  
>>> (scratch(0x15E4)=0xCAFEDEAD)
>>>  [drm:r100_cp_init] *ERROR* radeon: cp isn't working (-22).
>>>  radeon 0000:80:00.0: failed initializing CP (-22).
>>>  radeon 0000:80:00.0: Disabling GPU acceleration
>>>  [drm:r100_cp_fini] *ERROR* Wait for CP idle timeout, shutting  
>>> down CP.
>>>  [drm] radeon: cp finalized
>>>  [drm] radeon: cp finalized

Have you tried agpmode=-1 to force PCI mode.  It seems like this was a  
problem at one time on ubuntu:
http://phoronix.com/forums/showthread.php?17615-Testing-radeon-KMS-on-Ubuntu

Dave
--
John David Anglin	dave.anglin@bell.net



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diff mbox

Patch

diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 65fb4cb..b07720f 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -74,10 +74,13 @@  EXPORT_SYMBOL(flush_cache_all_local);
 void
 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
-	struct page *page = pte_page(*ptep);
+	struct page *page;
 
-	if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
-	    test_bit(PG_dcache_dirty, &page->flags)) {
+	if (!pfn_valid(pte_pfn(*ptep)))
+		return;
+
+	page = pte_page(*ptep);
+	if (page_mapping(page) && test_bit(PG_dcache_dirty, &page->flags)) {
 
 		flush_kernel_dcache_page(page);
 		clear_bit(PG_dcache_dirty, &page->flags);
@@ -519,8 +522,9 @@  void flush_cache_mm(struct mm_struct *mm)
 					pte_t *ptep = get_ptep(pgd, addr);
 					if (ptep != NULL) {
 						pte_t pte = *ptep;
-						__flush_cache_page(vma, addr,
-						  page_to_phys(pte_page(pte)));
+						if (pfn_valid(pte_pfn(pte)))
+							__flush_cache_page(vma, addr,
+						  		page_to_phys(pte_page(pte)));
 					}
 				}
 			}