From patchwork Fri Mar 18 22:24:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 12785967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7893BC433F5 for ; Fri, 18 Mar 2022 22:24:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241270AbiCRW0H (ORCPT ); Fri, 18 Mar 2022 18:26:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233444AbiCRW0H (ORCPT ); Fri, 18 Mar 2022 18:26:07 -0400 Received: from cmx-mtlrgo002.bell.net (mta-mtl-001.bell.net [209.71.208.11]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5CCDBFD6DC for ; Fri, 18 Mar 2022 15:24:47 -0700 (PDT) X-RG-CM-BuS: 0 X-RG-CM-SC: 0 X-RG-CM: Clean X-Originating-IP: [70.50.7.94] X-RG-Env-Sender: dave.anglin@bell.net X-RG-Rigid: 621D9CE9021538AA X-CM-Envelope: MS4xfKRyiWJQs/uLHIaIUXFmci40jaAveJqv8gLHfXObwX3FoGdRuTcGKe64tNV6wmloCupub7OqQJQPsKY2EaY/kUEkxskCLJbpGFNFzZ7iNJ1boRopI16z r+h6FvzmcEMzKvQG494eb8hSZYGonOnr8Zg4Zky2+ru7ImCtxsRhG51nY+CVL7GdLiyOrN8dJCYOChgPvffKEmzQmxGin1TR4sQwJE6Ny3w/4v76zk4JlBLo RghwKStVt4mZZfmhTbHHCqIenyinklHlbU106/JJYX9oDo5Gr3GsnQ2SdzVFYWa9idaz/FaxR4lU6WYjHe7VopLD/qijA54Ly9bbjBcgW8/X/OlYKlU54djY o7BHpO5tnAkOz7KuFYBrbghWUm2Ki9+0Y3KAs4hFdqZErnQnwNioDPXPri7Y+Xv5Wh3v40dOm9MoE7UU1HIT4w1oTvW+mzrLe5hthVWlpRux0QjzZgxjBtJ4 anxtU9Pqzx0ZRirYOowKskmqf0kEynDjkfjEIlTw+G+1k/pP+p280kqXzI6DoNXe0AWh2pwAg6KlF2W2aVRY80UirYcWl2jN8OHdCbGCDUNHe9E/ak4+E64J 5xOfkxiL+7wh/rbOst2UWpxqHxS5SBTooBBmGtjdkIV8Tw== X-CM-Analysis: v=2.4 cv=aKWTFZxm c=1 sm=1 tr=0 ts=62350697 a=9k1bCY7nR7m1ZFzoCuQ56g==:117 a=9k1bCY7nR7m1ZFzoCuQ56g==:17 a=o8Y5sQTvuykA:10 a=FBHGMhGWAAAA:8 a=Q2245be5OrS5l0onsbsA:9 a=CjuIK1q_8ugA:10 a=TU7ha1VK5XSi81ZK5zAA:9 a=FfaGCDsud1wA:10 a=9gvnlMMaQFpL9xblJ6ne:22 Received: from mx3210.localdomain (70.50.7.94) by cmx-mtlrgo002.bell.net (5.8.807) (authenticated as dave.anglin@bell.net) id 621D9CE9021538AA; Fri, 18 Mar 2022 18:24:23 -0400 Received: by mx3210.localdomain (Postfix, from userid 1000) id 72D02220115; Fri, 18 Mar 2022 22:24:22 +0000 (UTC) Date: Fri, 18 Mar 2022 22:24:22 +0000 From: John David Anglin To: linux-parisc@vger.kernel.org Cc: Helge Deller , Deller , James Bottomley Subject: [PATCH] parisc: Fix invalidate/flush vmap routines Message-ID: MIME-Version: 1.0 Content-Disposition: inline Precedence: bulk List-ID: X-Mailing-List: linux-parisc@vger.kernel.org Cache move-in for virtual accesses is controlled by the TLB. Thus, we must generally purge TLB entries before flushing. The flush routines must use TLB entries that inhibit cache move-in. Signed-off-by: John David Anglin diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c index 94150b91c96f..a7c68d14ba94 100644 --- a/arch/parisc/kernel/cache.c +++ b/arch/parisc/kernel/cache.c @@ -633,16 +619,23 @@ void flush_kernel_vmap_range(void *vaddr, int size) { unsigned long start = (unsigned long)vaddr; unsigned long end = start + size; + unsigned long physaddr; + flush_tlb_kernel_range(start, end); if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) && (unsigned long)size >= parisc_cache_flush_threshold) { - flush_tlb_kernel_range(start, end); flush_data_cache(); return; } - flush_kernel_dcache_range_asm(start, end); - flush_tlb_kernel_range(start, end); + preempt_disable(); + while (start <= end) { + physaddr = lpa(start); + if (physaddr) + flush_dcache_page_asm(physaddr, start); + start += PAGE_SIZE; + } + preempt_enable(); } EXPORT_SYMBOL(flush_kernel_vmap_range); @@ -650,15 +643,22 @@ void invalidate_kernel_vmap_range(void *vaddr, int size) { unsigned long start = (unsigned long)vaddr; unsigned long end = start + size; + unsigned long physaddr; + flush_tlb_kernel_range(start, end); if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) && (unsigned long)size >= parisc_cache_flush_threshold) { - flush_tlb_kernel_range(start, end); flush_data_cache(); return; } - purge_kernel_dcache_range_asm(start, end); - flush_tlb_kernel_range(start, end); + preempt_disable(); + while (start <= end) { + physaddr = lpa(start); + if (physaddr) + purge_dcache_page_asm(physaddr, start); + start += PAGE_SIZE; + } + preempt_enable(); } EXPORT_SYMBOL(invalidate_kernel_vmap_range);