| Message ID | ZGJ7bTYEBGtYMNiA@p100 (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [RFC] more progress with radeon on C8000 | expand |
* Helge Deller <deller@gmx.de>: > There have been various approaches to fix the radeon graphic cards > on C8000 workstations, e.g. this is the last thread: > https://marc.info/?l=linux-parisc&m=156971832128700&w=2 > > With the patch below the radeon ring and ib tests don't fail any longer. > It uses (relatively) lightweight pdc/fdc instructions. > > The patch below > - uses the pdc instruction (purge data cache) before reading back the > ring test result from memory. > - modifies the parisc-agp code, based on Thomas patch > > The patch is not intended to by applied as-is. attached is a cleaned up version of the patch. With that a Radeon PCI card successfully initializes the rings. ATI FireGL X1 AGP card doesn't work yet, although I start to believe it's a problem with the card in general (R300), e.g. it reports "Generation 1 PCI interface in multifunction mode" diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c index d68d05d5d383..4d644c267d3f 100644 --- a/drivers/char/agp/parisc-agp.c +++ b/drivers/char/agp/parisc-agp.c @@ -90,6 +90,9 @@ parisc_agp_tlbflush(struct agp_memory *mem) { struct _parisc_agp_info *info = &parisc_agp_info; + /* force fdc ops to be visible to IOMMU */ + asm_io_sync(); + writeq(info->gart_base | ilog2(info->gart_size), info->ioc_regs+IOC_PCOM); readq(info->ioc_regs+IOC_PCOM); /* flush */ } @@ -158,6 +161,7 @@ parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type) info->gatt[j] = parisc_agp_mask_memory(agp_bridge, paddr, type); + asm_io_fdc(&info->gatt[j]); } } @@ -191,7 +195,16 @@ static unsigned long parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr, int type) { - return SBA_PDIR_VALID_BIT | addr; + unsigned ci; /* coherent index */ + dma_addr_t pa; + + pa = addr & IOVP_MASK; + asm("lci 0(%1), %0" : "=r" (ci) : "r" (phys_to_virt(pa))); + + pa |= (ci >> PAGE_SHIFT) & 0xff;/* move CI (8 bits) into lowest byte */ + pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */ + + return cpu_to_le64(pa); } static void diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 7051c9c909c2..a84eba2fb429 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,8 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n"); +#elif defined(CONFIG_PARISC) + flush_kernel_dcache_range((unsigned long) addr, length); #else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index d4f09ecc3d22..45711c9b7cfe 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -642,6 +642,10 @@ void r100_hpd_fini(struct radeon_device *rdev) */ void r100_pci_gart_tlb_flush(struct radeon_device *rdev) { + /* flush gtt[] gart table entries from r100_pci_gart_set_page() */ + dma_sync_single_for_device(&rdev->pdev->dev, rdev->gart.table_addr, + rdev->gart.table_size, DMA_TO_DEVICE); + /* TODO: can we do somethings here ? */ /* It seems hw only cache one entry so we should discard this * entry otherwise if first GPU GART read hit this entry it diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index 7e207276df37..35652286244d 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c @@ -29,6 +29,7 @@ #include <drm/drm_device.h> #include <drm/drm_file.h> +#include <drm/drm_cache.h> #include "radeon.h" @@ -177,6 +178,9 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring, radeon_ring_write(ring, ring->nop); } mb(); + if (IS_ENABLED(CONFIG_PARISC)) + drm_clflush_virt_range((void *)&ring->ring[0], ring->wptr * sizeof(uint32_t)); + /* If we are emitting the HDP flush via MMIO, we need to do it after * all CPU writes to VRAM finished. */
On 2023-05-16 4:48 p.m., Helge Deller wrote: > * Helge Deller<deller@gmx.de>: >> There have been various approaches to fix the radeon graphic cards >> on C8000 workstations, e.g. this is the last thread: >> https://marc.info/?l=linux-parisc&m=156971832128700&w=2 >> >> With the patch below the radeon ring and ib tests don't fail any longer. >> It uses (relatively) lightweight pdc/fdc instructions. >> >> The patch below >> - uses the pdc instruction (purge data cache) before reading back the >> ring test result from memory. >> - modifies the parisc-agp code, based on Thomas patch >> >> The patch is not intended to by applied as-is. > attached is a cleaned up version of the patch. I tried this change on c8000 with kernel 6.3.3: [ 89.531274] drm_kms_helper alternatives: applied 0 out of 27 patches [ 89.630885] ipmi_si alternatives: applied 0 out of 8 patches [ 89.731041] ipmi_si: IPMI System Interface driver [ 89.821872] drm_display_helper alternatives: applied 0 out of 6 patches [ 89.833885] ipmi_si: Adding device-tree-specified kcs state machine [ 89.971367] ipmi_si: Trying device-tree-specified kcs state machine at mem address 0xfffffff0f05b0000, slave address 0x0, irq 0 [ 90.271358] ttm alternatives: applied 0 out of 13 patches [ 90.421083] drm_ttm_helper alternatives: applied 0 out of 2 patches [ 90.881506] radeon alternatives: applied 0 out of 4803 patches [ 90.980838] [drm] radeon kernel modesetting enabled. [ 91.041955] [drm] initializing kernel modesetting (RV350 0x1002:0x4154 0x1002:0x0002 0x80). [ 91.140773] [drm] Forcing AGP to PCI mode [ 91.290915] [drm] GPU not posted. posting now... [ 91.551801] [drm] Generation 2 PCI interface, using max accessible memory [ 91.620801] radeon 0000:80:00.0: VRAM: 128M 0xFFFFFFFFC0000000 - 0xFFFFFFFFC7FFFFFF (128M used) [ 91.671141] ipmi 16: IPMI message handler: Found new BMC (man_id: 0x00000b, prod_id: 0x8201, dev_id: 0x32) [ 91.710747] radeon 0000:80:00.0: GTT: 512M 0xFFFFFFFFA0000000 - 0xFFFFFFFFBFFFFFFF [ 91.814064] ipmi 16: IPMI kcs interface initialized [ 91.880842] [drm] Detected VRAM RAM=128M, BAR=128M [ 91.970765] [drm] RAM width 128bits DDR [ 91.971192] [drm] radeon: 128M of VRAM memory ready [ 92.050830] [drm] radeon: 512M of GTT memory ready. [ 92.110946] [drm] GART: num cpu pages 131072, num gpu pages 131072 [ 92.222903] [drm] radeon: 1 quad pipes, 1 Z pipes initialized [ 92.290747] [drm] PCI GART of 512M enabled (table at 0x0000000047040000). [ 92.370907] radeon 0000:80:00.0: WB enabled [ 92.431273] radeon 0000:80:00.0: fence driver on ring 0 use gpu addr 0xffffffffa0000000 [ 92.531273] [drm] radeon: irq initialized. [ 92.560906] [drm] Loading R300 Microcode [ 92.631141] radeon 0000:80:00.0: Direct firmware load for radeon/R300_cp.bin failed with error -2 [ 92.743052] radeon_cp: Failed to load firmware "radeon/R300_cp.bin" [ 92.819159] [drm:r100_cp_init [radeon]] *ERROR* Failed to load firmware! [ 92.890738] radeon 0000:80:00.0: failed initializing CP (-2). [ 92.960765] radeon 0000:80:00.0: Disabling GPU acceleration [ 93.030744] [drm] radeon: cp finalized [ 93.142149] [drm] Radeon Display Connectors [ 93.170762] [drm] Connector 0: [ 93.170771] [drm] VGA-1 [ 93.170775] [drm] DDC: 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 [ 93.170786] [drm] Encoders: [ 93.290760] [drm] CRT1: INTERNAL_DAC1 [ 93.340770] [drm] Connector 1: [ 93.380749] [drm] DVI-I-1 [ 93.410745] [drm] HPD1 [ 93.440846] [drm] DDC: 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 [ 93.520737] [drm] Encoders: [ 93.559678] [drm] CRT2: INTERNAL_DAC2 [ 93.590733] [drm] DFP1: INTERNAL_TMDS1 [ 93.853779] [drm] fb mappable at 0xFFFFFFFFC0040000 [ 93.900758] [drm] vram apper at 0xFFFFFFFFC0000000 [ 93.940732] [drm] size 5242880 [ 93.960731] [drm] fb depth is 24 [ 93.981757] [drm] pitch is 5120 [ 94.080657] Console: switching to colour frame buffer device 160x64 [ 94.290810] radeon 0000:80:00.0: [drm] fb0: radeondrmfb frame buffer device [ 94.420892] [drm] Initialized radeon 2.50.0 20080528 for 0000:80:00.0 on minor 0 80:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] RV350 GL [FireGL T2] (rev 80) (prog-if 00 [VGA controller]) Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] RV350 GL [FireGL T2] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 192 (2000ns min), Cache Line Size: 128 bytes Interrupt: pin A routed to IRQ 75 Region 0: Memory at ffffffffc0000000 (32-bit, prefetchable) [size=128M] Region 1: I/O ports at 3c000 [size=256] Region 2: Memory at ffffffffc8020000 (32-bit, non-prefetchable) [size=64K] Expansion ROM at ffffffffc8000000 [disabled] [size=128K] Capabilities: <access denied> Kernel driver in use: radeon Kernel modules: radeon Firmware still fails to load and acceleration is disabled. Maybe this is also a cache flush issue? FB console looks okay. This is a significant advance
On 5/17/23 21:59, John David Anglin wrote: > On 2023-05-16 4:48 p.m., Helge Deller wrote: >> * Helge Deller<deller@gmx.de>: >>> There have been various approaches to fix the radeon graphic cards >>> on C8000 workstations, e.g. this is the last thread: >>> https://marc.info/?l=linux-parisc&m=156971832128700&w=2 >>> >>> With the patch below the radeon ring and ib tests don't fail any longer. >>> It uses (relatively) lightweight pdc/fdc instructions. >>> >>> The patch below >>> - uses the pdc instruction (purge data cache) before reading back the >>> ring test result from memory. >>> - modifies the parisc-agp code, based on Thomas patch >>> >>> The patch is not intended to by applied as-is. >> attached is a cleaned up version of the patch. > I tried this change on c8000 with kernel 6.3.3: > > [ 89.531274] drm_kms_helper alternatives: applied 0 out of 27 patches > [ 89.630885] ipmi_si alternatives: applied 0 out of 8 patches > [ 89.731041] ipmi_si: IPMI System Interface driver > [ 89.821872] drm_display_helper alternatives: applied 0 out of 6 patches > [ 89.833885] ipmi_si: Adding device-tree-specified kcs state machine > [ 89.971367] ipmi_si: Trying device-tree-specified kcs state machine at mem address 0xfffffff0f05b0000, slave address 0x0, irq 0 > [ 90.271358] ttm alternatives: applied 0 out of 13 patches > [ 90.421083] drm_ttm_helper alternatives: applied 0 out of 2 patches > [ 90.881506] radeon alternatives: applied 0 out of 4803 patches > [ 90.980838] [drm] radeon kernel modesetting enabled. > [ 91.041955] [drm] initializing kernel modesetting (RV350 0x1002:0x4154 0x1002:0x0002 0x80). > [ 91.140773] [drm] Forcing AGP to PCI mode > [ 91.290915] [drm] GPU not posted. posting now... > [ 91.551801] [drm] Generation 2 PCI interface, using max accessible memory > [ 91.620801] radeon 0000:80:00.0: VRAM: 128M 0xFFFFFFFFC0000000 - 0xFFFFFFFFC7FFFFFF (128M used) > [ 91.671141] ipmi 16: IPMI message handler: Found new BMC (man_id: 0x00000b, prod_id: 0x8201, dev_id: 0x32) > [ 91.710747] radeon 0000:80:00.0: GTT: 512M 0xFFFFFFFFA0000000 - 0xFFFFFFFFBFFFFFFF > [ 91.814064] ipmi 16: IPMI kcs interface initialized > [ 91.880842] [drm] Detected VRAM RAM=128M, BAR=128M > [ 91.970765] [drm] RAM width 128bits DDR > [ 91.971192] [drm] radeon: 128M of VRAM memory ready > [ 92.050830] [drm] radeon: 512M of GTT memory ready. > [ 92.110946] [drm] GART: num cpu pages 131072, num gpu pages 131072 > [ 92.222903] [drm] radeon: 1 quad pipes, 1 Z pipes initialized > [ 92.290747] [drm] PCI GART of 512M enabled (table at 0x0000000047040000). > [ 92.370907] radeon 0000:80:00.0: WB enabled > [ 92.431273] radeon 0000:80:00.0: fence driver on ring 0 use gpu addr 0xffffffffa0000000 > [ 92.531273] [drm] radeon: irq initialized. > [ 92.560906] [drm] Loading R300 Microcode > [ 92.631141] radeon 0000:80:00.0: Direct firmware load for radeon/R300_cp.bin failed with error -2 > [ 92.743052] radeon_cp: Failed to load firmware "radeon/R300_cp.bin" > [ 92.819159] [drm:r100_cp_init [radeon]] *ERROR* Failed to load firmware! > [ 92.890738] radeon 0000:80:00.0: failed initializing CP (-2). > [ 92.960765] radeon 0000:80:00.0: Disabling GPU acceleration > [ 93.030744] [drm] radeon: cp finalized > [ 93.142149] [drm] Radeon Display Connectors > [ 93.170762] [drm] Connector 0: > [ 93.170771] [drm] VGA-1 > [ 93.170775] [drm] DDC: 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 > [ 93.170786] [drm] Encoders: > [ 93.290760] [drm] CRT1: INTERNAL_DAC1 > [ 93.340770] [drm] Connector 1: > [ 93.380749] [drm] DVI-I-1 > [ 93.410745] [drm] HPD1 > [ 93.440846] [drm] DDC: 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 > [ 93.520737] [drm] Encoders: > [ 93.559678] [drm] CRT2: INTERNAL_DAC2 > [ 93.590733] [drm] DFP1: INTERNAL_TMDS1 > [ 93.853779] [drm] fb mappable at 0xFFFFFFFFC0040000 > [ 93.900758] [drm] vram apper at 0xFFFFFFFFC0000000 > [ 93.940732] [drm] size 5242880 > [ 93.960731] [drm] fb depth is 24 > [ 93.981757] [drm] pitch is 5120 > [ 94.080657] Console: switching to colour frame buffer device 160x64 > [ 94.290810] radeon 0000:80:00.0: [drm] fb0: radeondrmfb frame buffer device > [ 94.420892] [drm] Initialized radeon 2.50.0 20080528 for 0000:80:00.0 on minor 0 > > 80:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] RV350 GL [FireGL T2] (rev 80) (prog-if 00 [VGA controller]) > Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] RV350 GL [FireGL T2] > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- > Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- > Latency: 192 (2000ns min), Cache Line Size: 128 bytes > Interrupt: pin A routed to IRQ 75 > Region 0: Memory at ffffffffc0000000 (32-bit, prefetchable) [size=128M] > Region 1: I/O ports at 3c000 [size=256] > Region 2: Memory at ffffffffc8020000 (32-bit, non-prefetchable) [size=64K] > Expansion ROM at ffffffffc8000000 [disabled] [size=128K] > Capabilities: <access denied> > Kernel driver in use: radeon > Kernel modules: radeon > > Firmware still fails to load You need to install the debian firware package: apt install firmware-linux-nonfree firmware-linux-free > and acceleration is disabled. Yes, if firware isn't loaded the acceleration will be disabled too. But even with firmware loaded the ring tests will fail on AGP cards. > Maybe this is also a cache flush issue? Probably. Interestingly the radeon driver doesn't use the parisc-agp driver, but it's internal GART. Since it works with radeon-PCI cards, maybe it's not useable on parisc and we would need the parisc-agp driver. > FB console looks okay. > > This is a significant advance
On 2023-05-17 4:44 p.m., Helge Deller wrote: >> Firmware still fails to load > > You need to install the debian firware package: > apt install firmware-linux-nonfree firmware-linux-free Thanks. Firmware now loads. > >> and acceleration is disabled. > > Yes, if firware isn't loaded the acceleration will be disabled too. > But even with firmware loaded the ring tests will fail on AGP cards. Yes, ring tests still fail. Dave
diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c index d68d05d5d383..1b1bea33c767 100644 --- a/drivers/char/agp/parisc-agp.c +++ b/drivers/char/agp/parisc-agp.c @@ -158,6 +158,7 @@ parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type) info->gatt[j] = parisc_agp_mask_memory(agp_bridge, paddr, type); + asm_io_fdc(&info->gatt[j]); } } @@ -191,7 +192,16 @@ static unsigned long parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr, int type) { - return SBA_PDIR_VALID_BIT | addr; + unsigned ci; /* coherent index */ + u64 pa; + + pa = addr & IOVP_MASK; + asm("lci 0(%1), %0" : "=r" (ci) : "r" (__va(pa))); + + pa |= (ci >> PAGE_SHIFT) & 0xff;/* move CI (8 bits) into lowest byte */ + pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */ + + return cpu_to_le64(pa); } static void diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index d4f09ecc3d22..c4a73a5a3651 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c @@ -710,6 +710,7 @@ void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, { u32 *gtt = rdev->gart.ptr; gtt[i] = cpu_to_le32(lower_32_bits(entry)); + asm_io_fdc(>t[i]); } void r100_pci_gart_fini(struct radeon_device *rdev) @@ -3689,6 +3690,16 @@ void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) { struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; + u32 *ptr; + int len; + ptr = ib->ptr; + len = ib->length_dw; + while (len >= 0) { + asm_io_fdc(ptr); + ptr++; + len--; + } + if (ring->rptr_save_reg) { u32 next_rptr = ring->wptr + 2 + 3; radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 8afb03bbce29..45991d26be6a 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -2463,16 +2463,20 @@ static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, bool always_indirect) { /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ - if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) + if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) { + asm volatile("pdc %%r0(%0)" : : "r" (((void __iomem *)rdev->rmmio) + reg) : "memory"); return readl(((void __iomem *)rdev->rmmio) + reg); + } else return r100_mm_rreg_slow(rdev, reg); } static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, bool always_indirect) { - if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) + if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) { writel(v, ((void __iomem *)rdev->rmmio) + reg); + asm_io_fdc(((void __iomem *)rdev->rmmio) + reg); + } else r100_mm_wreg_slow(rdev, reg, v); } @@ -2683,7 +2687,9 @@ static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) if (ring->count_dw <= 0) DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); - ring->ring[ring->wptr++] = v; + ring->ring[ring->wptr] = v; + asm_io_fdc(&ring->ring[ring->wptr]); + ring->wptr++; ring->wptr &= ring->ptr_mask; ring->count_dw--; ring->ring_free_dw--;
There have been various approaches to fix the radeon graphic cards on C8000 workstations, e.g. this is the last thread: https://marc.info/?l=linux-parisc&m=156971832128700&w=2 With the patch below the radeon ring and ib tests don't fail any longer. It uses (relatively) lightweight pdc/fdc instructions. The patch below - uses the pdc instruction (purge data cache) before reading back the ring test result from memory. - modifies the parisc-agp code, based on Thomas patch The patch is not intended to by applied as-is. The log below is from an ATI radeon PCI card, so the AGP patch isn't used here. I wonder if there is a simple testcase available to check if everything works? [ 104.571313] [drm] radeon kernel modesetting enabled. [ 104.643912] radeon 0000:60:04.0: enabling SERR and PARITY (0107 -> 0147) [ 104.737658] [drm] initializing kernel modesetting (RV280 0x1002:0x5965 0x1002:0x2002 0x01). [ 104.950370] [drm] GPU not posted. posting now... [ 105.031735] [drm] Generation 2 PCI interface, using max accessible memory [ 105.111315] radeon 0000:60:04.0: VRAM: 64M 0xFFFFFFFFB4000000 - 0xFFFFFFFFB7FFFFFF (64M used) [ 105.216120] radeon 0000:60:04.0: GTT: 512M 0xFFFFFFFF94000000 - 0xFFFFFFFFB3FFFFFF [ 105.304810] [drm] Detected VRAM RAM=64M, BAR=64M [ 105.361061] [drm] RAM width 64bits DDR [ 105.410312] [drm] radeon: 64M of VRAM memory ready [ 105.465816] [drm] radeon: 512M of GTT memory ready. [ 105.526336] [drm] GART: num cpu pages 131072, num gpu pages 131072 [ 105.628966] [drm] PCI GART of 512M enabled (table at 0x000000004B2C0000). [ 105.707636] radeon 0000:60:04.0: WB disabled [ 105.759884] radeon 0000:60:04.0: fence driver on ring 0 use gpu addr 0xffffffff94000000 [ 105.864222] [drm] radeon: irq initialized. [ 105.912906] [drm] Loading R200 Microcode [ 105.997513] [drm] radeon: ring at 0xFFFFFFFF94001000 [ 106.057793] [drm] ring test succeeded in 0 usecs [ 106.126386] [drm] ib test succeeded in 0 usecs [ 106.183780] [drm] Radeon Display Connectors [ 106.230816] [drm] Connector 0: [ 106.271052] [drm] DVI-I-1 [ 106.303247] [drm] HPD2 [ 106.335433] [drm] DDC: 0x60 0x60 0x60 0x60 0x60 0x60 0x60 0x60 [ 106.407906] [drm] Encoders: [ 106.440118] [drm] CRT1: INTERNAL_DAC1 [ 106.488393] [drm] DFP2: INTERNAL_DVO1 [ 106.540706] [drm] Connector 1: [ 106.577071] [drm] DVI-I-2 [ 106.609150] [drm] HPD1 [ 106.641325] [drm] DDC: 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 [ 106.713770] [drm] Encoders: [ 106.749996] [drm] CRT2: INTERNAL_DAC2 [ 106.798295] [drm] DFP1: INTERNAL_TMDS1 [ 106.846639] [drm] Initialized radeon 2.50.0 20080528 for 0000:60:04.0 on minor 0 [ 107.482694] [drm] fb mappable at 0xFFFFFFFFB4040000 [ 107.538318] [drm] vram apper at 0xFFFFFFFFB4000000 [ 107.598634] [drm] size 9216000 [ 107.634831] [drm] fb depth is 24 [ 107.675046] [drm] pitch is 7680 [ 108.042812] Console: switching to colour frame buffer device 240x67 [ 108.531201] radeon 0000:60:04.0: [drm] fb0: radeondrmfb frame buffer device Signed-off-by: Helge Deller <deller@gmx.de>