From patchwork Tue Mar 26 15:13:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 10871363 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5E48D14DE for ; Tue, 26 Mar 2019 15:14:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4900628C79 for ; Tue, 26 Mar 2019 15:14:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3AC9C28E12; Tue, 26 Mar 2019 15:14:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8CFCD28C79 for ; Tue, 26 Mar 2019 15:14:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731546AbfCZPOM (ORCPT ); Tue, 26 Mar 2019 11:14:12 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:4905 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726175AbfCZPOL (ORCPT ); Tue, 26 Mar 2019 11:14:11 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 08:14:05 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 08:14:09 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 08:14:09 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 26 Mar 2019 15:14:09 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 26 Mar 2019 15:14:09 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 26 Mar 2019 15:14:09 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 08:14:08 -0700 From: Vidya Sagar To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 00/10] Add Tegra194 PCIe support Date: Tue, 26 Mar 2019 20:43:17 +0530 Message-ID: <1553613207-3988-1-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553613245; bh=ncXaSa4ThiFNCkuvW++HZE9kMEIyuki412uebWwSdMA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=nDWCsMd0jWGHY93voLkaVqoShFd+mdgb96SNkQaBIpvOiWc/U+zQ36aASdFWzRKII eRqKCgCaeol2kkzMSVRiBMdm6MCewP99veCU4EwnxMlgP2kUb0PwQsNf7o1Keb6aB9 CYBX9GiiKDc04ORCgYTSi6+TwOTAUJpCya6dl0391O3c9VtR61rzljJzbLnKZy/dbe /F9BtzFDLNKPBTN6EIbIqSXn6wejd6UiYE8JNWxzXEFv0R83/YrNnSO2Yr9WvjO1D9 o1FgGdx/a1grQKzVGOmd1rdNOxApz3Yz1pXg0SNEDmF5Mr3XcAvRr+VEKwthxSV/Xp id1n20kxyjoTA== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra194 has six PCIe controllers based on Synopsys DesignWare core. There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO: Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively. Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each PCIe controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bricks) to PCIe controller This patch series - Adds support for P2U PHY driver - Adds support for PCIe host controller - Adds device tree nodes each PCIe controllers - Enables nodes applicable to p2972-0000 platform - Adds helper APIs in Designware core driver to get capability regs offset - Adds defines for new feature registers of PCIe spec revision 4 - Makes changes in DesignWare core driver to get Tegra194 PCIe working Testing done on P2972-0000 platform - Able to get PCIe link up with on-board Marvel eSATA controller - Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot - Able to do data transfers with both SATA drives and NVMe cards Note - Enabling x8 slot on P2972-0000 platform requires pinmux driver for Tegra194. It is being worked on currently and hence Controller:5 (i.e. x8 slot) is disabled in this patch series. A future patch series would enable this. Vidya Sagar (10): PCI: save pci_bus pointer in pcie_port structure PCI: perform dbi regs write lock towards the end PCI: dwc: Move config space capability search API PCI: Add #defines for PCIe spec r4.0 features dt-bindings: PCI: tegra: Add device tree support for T194 arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT arm64: tegra: Enable PCIe slots in P2972-0000 board phy: tegra: Add PCIe PIPE2UPHY support PCI: tegra: Add Tegra194 PCIe support arm64: Add Tegra194 PCIe driver to defconfig .../bindings/pci/nvidia,tegra194-pcie.txt | 209 +++ .../devicetree/bindings/phy/phy-tegra194-p2u.txt | 34 + arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 50 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 473 +++++ arch/arm64/configs/defconfig | 1 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-designware-ep.c | 37 +- drivers/pci/controller/dwc/pcie-designware-host.c | 4 +- drivers/pci/controller/dwc/pcie-designware.c | 73 + drivers/pci/controller/dwc/pcie-designware.h | 4 + drivers/pci/controller/dwc/pcie-tegra194.c | 1862 ++++++++++++++++++++ drivers/phy/tegra/Kconfig | 7 + drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/pcie-p2u-tegra194.c | 138 ++ include/uapi/linux/pci_regs.h | 22 +- 17 files changed, 2888 insertions(+), 40 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c create mode 100644 drivers/phy/tegra/pcie-p2u-tegra194.c