From patchwork Tue Aug 13 07:42:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 13761500 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59277225AF; Tue, 13 Aug 2024 08:02:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723536151; cv=none; b=cQDzy7q1dWMpbRoPdFjjv6OB0pXKAU5oK+09ZeM4ab98zSMNxXRIMqhqiP9C6A6jE4VyS5zXrPtZ1a30KVyniefNkg7DYZWUNvCWkHJ+cDHNLM0sR7UtuYNl9E4PEIFY0upuaZvexYUh7Pe+dIfXD4RWFK5xjq5hUlb4ZXBM/f4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723536151; c=relaxed/simple; bh=aNolctlY4FEkPyrq8h+vaS63dt/bh8uyQNVMknBP/j8=; h=From:To:Cc:Subject:Date:Message-Id; b=EHmHkzoNeSCDRpH6ZbD1JanPkUD8zplo8bLnkctFEVa0C3Q3Xm49g92xKCxIPqNN1whbMkFxGXB/1e2ekkNro/USIMxp0E/Gn3wCY3BoI53siJKcl84FzQI42AcC0/BHiN+LZ0/bAiPEUjVi0SLUa65Fpx5VfLJaCMsV7XqK/0g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 674041A1138; Tue, 13 Aug 2024 10:02:23 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2D0141A1188; Tue, 13 Aug 2024 10:02:23 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 8C04E181D0FD; Tue, 13 Aug 2024 16:02:21 +0800 (+08) From: Richard Zhu To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, l.stach@pengutronix.de Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v5 0/4] Add dbi2 and atu for i.MX8M PCIe EP Date: Tue, 13 Aug 2024 15:42:19 +0800 Message-Id: <1723534943-28499-1-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: v5 changes: - Correct subject prefix. v4 changes: - Add Frank's reviewed tag, and re-format the commit message. v3 changes: - Refine the commit descriptions. v2 changes: Thanks for Conor's comments. - Place the new added properties at the end. Ideally, dbi2 and atu base addresses should be fetched from DT. Add dbi2 and atu base addresses for i.MX8M PCIe EP here. [PATCH v5 1/4] dt-bindings: imx6q-pcie: Add reg-name "dbi2" and "atu" [PATCH v5 2/4] arm64: dts: imx8mq: Add dbi2 and atu reg for i.MX8MQ [PATCH v5 3/4] arm64: dts: imx8mp: Add dbi2 and atu reg for i.MX8MP [PATCH v5 4/4] arm64: dts: imx8mm: Add dbi2 and atu reg for i.MX8MM Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 13 +++++++++---- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 +++++--- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 +++++-- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 +++++--- 4 files changed, 24 insertions(+), 12 deletions(-)