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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id m65sm53062646pfg.180.2019.01.24.12.15.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 24 Jan 2019 12:15:39 -0800 (PST) From: Andrey Smirnov To: Lorenzo Pieralisi Cc: Andrey Smirnov , Bjorn Helgaas , Fabio Estevam , Chris Healy , Lucas Stach , Leonard Crestez , "A.s. Dong" , Richard Zhu , linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v6 0/4] PCIE support for i.MX8MQ Date: Thu, 24 Jan 2019 12:15:18 -0800 Message-Id: <20190124201522.8973-1-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Everyone: This series contains changes I made in order to enable support of PCIE IP block on i.MX8MQ SoCs. Changes since [v5]: - Reformatted commit messages to adhere to https://lore.kernel.org/linux-pci/20171026223701.GA25649@bhelgaas-glaptop.roam.corp.google.com/ Changes since [v4]: - Collected Reviewed-by from Lucas - Replaced ((ARM || ARM64) && COMPILE_TEST) with COMPILE_TEST as per suggestion from Rob Changes since [v3]: - Based on feedback from NXP, DIRECT_SPEED_CHANGE quirk was expanded to cover both i.MX7 and i.MX8MQ - Code setting device type in GPR12 moved to a standalone function - Explicit "fsl,controller-id" binding was dropped, replaced by using controller physical address to determine logical ID - Dropped Reviewed-by from Lucas for patch 4/4 due to the change above (haven't heard explicit "yea" for it from him) Changes since [v2], [fixes]: - Incorporated [patch] introducing drvdata - i.MX6 PHY operation gating converted to a single patch and to use a dedicated flag instead of doing explicit variant check - Kconfig entry changed to use ARM64 && ARCH_MXC - Dropped FALLTHROUGH annotations Changes since [v1]: - Driver changed to use single "fsl,controller-id" property to distinguish between two intances of PCIE IP block - All code pertaining to L1SS was dropped to simplify the patch - Documented additions to DT bindings Feedback is welcome! Thanks, Andrey Smirnov [v4] https://lore.kernel.org/linux-arm-kernel/20190104165335.13205-1-andrew.smirnov@gmail.com [v3] https://lore.kernel.org/linux-arm-kernel/20181218040702.29231-1-andrew.smirnov@gmail.com [patch] https://patchwork.kernel.org/patch/10712261/ [fixes] https://lore.kernel.org/linux-arm-kernel/20181216230916.22982-1-andrew.smirnov@gmail.com [v2] https://lore.kernel.org/linux-arm-kernel/20181206073545.10967-1-andrew.smirnov@gmail.com [v1] https://lore.kernel.org/linux-arm-kernel/20181117181225.10737-1-andrew.smirnov@gmail.com/ Andrey Smirnov (4): PCI: imx6: Introduce drvdata PCI: imx6: Mark PHY functions as i.MX6 specific PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flag PCI: imx6: Add support for i.MX8MQ .../bindings/pci/fsl,imx6q-pcie.txt | 3 +- drivers/pci/controller/dwc/Kconfig | 4 +- drivers/pci/controller/dwc/pci-imx6.c | 150 +++++++++++++++--- 3 files changed, 133 insertions(+), 24 deletions(-)