From patchwork Wed Aug 28 17:28:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 11119511 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3C6D81800 for ; Wed, 28 Aug 2019 17:29:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2561C22DA7 for ; Wed, 28 Aug 2019 17:29:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726583AbfH1R27 (ORCPT ); Wed, 28 Aug 2019 13:28:59 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:7367 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726315AbfH1R27 (ORCPT ); Wed, 28 Aug 2019 13:28:59 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 28 Aug 2019 10:29:00 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 28 Aug 2019 10:28:58 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 28 Aug 2019 10:28:58 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 28 Aug 2019 17:28:58 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 28 Aug 2019 17:28:58 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 28 Aug 2019 17:28:58 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 28 Aug 2019 10:28:57 -0700 From: Vidya Sagar To: , , , , , CC: , , , , , , , , , , , , Subject: [PATCH V3 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform Date: Wed, 28 Aug 2019 22:58:44 +0530 Message-ID: <20190828172850.19871-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch series enables Tegra194's C5 controller which owns x16 slot in p2972-0000 platform. C5 controller's PERST# and CLKREQ# are not configured as output and bi-directional signals by default and hence they need to be configured explicitly. Also, x16 slot's 3.3V and 12V supplies are controlled through GPIOs and hence they need to be enabled through regulator framework. This patch series adds required infrastructural support to address both the aforementioned requirements. Testing done on p2972-0000 platform - Able to enumerate devices connected to x16 slot (owned by C5 controller) - Enumerated device's functionality verified - Suspend-Resume sequence is verified with device connected to x16 slot DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1567013340; bh=TvQY7ZhhxcvoKbpcEAh6qHqIQEasISWH+/X/STdQQk0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=gVtBiB2IR+pKYaZJQ+f6BYQX23e2leD7q8vdf+vr0+12GlPQc/30oFhIDgzGmLr3W 81mgV2Pp3bLNf9oNOB7tnv+yjoJK+qPGAB0bQ+VPMKGOkpvVfFtN4K3D+TkNjEQnQc eBs35Pzc7zQ3jso4y80hoeIGegqfu4qLvORCW3qsy7OuPxjELUpGKvJTozekRSZVw3 voa570Uvaiotu9UgYqdAyJe0S4iuNUmJ8eWJDZLb9zkj1gfWhuQaDxt6bOMK8pyr7e SVhNP0p2cTOaV0ALtd16tvi7+vRmcV4uQeArl0l1XPwxwHkR6ShLYbyji3Zb+JxJGN vrTsP917B385w== V3: * Addressed some more review comments from Andrew Murray and Thierry Reding V2: * Changed the order of patches in the series for easy merging * Addressed review comments from Thierry Reding and Andrew Murray Vidya Sagar (6): dt-bindings: PCI: tegra: Add sideband pins configuration entries dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries PCI: tegra: Add support to configure sideband pins PCI: tegra: Add support to enable slot regulators arm64: tegra: Add configuration for PCIe C5 sideband signals arm64: tegra: Add PCIe slot supply information in p2972-0000 platform .../bindings/pci/nvidia,tegra194-pcie.txt | 16 ++++ .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 24 +++++ .../boot/dts/nvidia/tegra194-p2972-0000.dts | 4 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 +++++++- drivers/pci/controller/dwc/pcie-tegra194.c | 94 ++++++++++++++++++- 5 files changed, 172 insertions(+), 4 deletions(-)