From patchwork Thu Sep 10 06:11:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuanjia Liu X-Patchwork-Id: 11766677 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3CD54618 for ; Thu, 10 Sep 2020 06:13:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 167DE20882 for ; Thu, 10 Sep 2020 06:13:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="feV0DEPi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725996AbgIJGNh (ORCPT ); Thu, 10 Sep 2020 02:13:37 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:39774 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725885AbgIJGNf (ORCPT ); Thu, 10 Sep 2020 02:13:35 -0400 X-UUID: 0ce9efa0dd4b47d0872e5ee2db51bb94-20200910 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=zFcW3GcXd1P8FnAbyGNj9CaD7meMZ2kjh/WC5Wilqqw=; b=feV0DEPi/Pu4f5Psg3pKMetQDcIc1AJgj9rs0e0nhdp+ZEDcYxEbCiTo8dusziEx/zknMwyJGFgkVQU781y6jElQ3WTOxBoXlt93wkA53ZT5yjf0+fgX+8LPuSRZyup+O8AjVcjqiq1im3dXX/bhc/lKZIGckWH54Y3oabuQJQY=; X-UUID: 0ce9efa0dd4b47d0872e5ee2db51bb94-20200910 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 19333964; Thu, 10 Sep 2020 14:13:31 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 10 Sep 2020 14:13:28 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 10 Sep 2020 14:13:28 +0800 From: Chuanjia Liu To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi CC: , , , , , Frank Wunderlich , Ryder Lee Subject: [PATCH v5 0/4] Spilt PCIe node to comply with hardware design Date: Thu, 10 Sep 2020 14:11:11 +0800 Message-ID: <20200910061115.909-1-chuanjia.liu@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In current architecture, MSI domain will be inherited from the root bridge, and all of the devices will share the same MSI domain. Hence that, the PCIe devices will not work properly if the irq number which required is more than 32. Split the PCIe node for MT2712 and MT7622 platform to fix MSI issue and comply with the hardware design. change note: v5:rebase for 5.9-rc1, no code change. v4:change commit message due to bayes statistical bogofilter considers this series patch SPAM. v3:rebase for 5.8-rc1. Only collect ack of Ryder, No code change. v2:change the allocation of MT2712 PCIe MMIO space due to the allocation size is not right in v1. Chuanjia Liu (4): dt-bindings: pci: mediatek: Modified the Device tree bindings PCI: mediatek: Use regmap to get shared pcie-cfg base arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622 ARM: dts: mediatek: Modified MT7629 PCIe node .../bindings/pci/mediatek-pcie-cfg.yaml | 38 +++++ .../devicetree/bindings/pci/mediatek-pcie.txt | 144 +++++++++++------- arch/arm/boot/dts/mt7629-rfb.dts | 3 +- arch/arm/boot/dts/mt7629.dtsi | 23 +-- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 75 +++++---- .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 16 +- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 6 +- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 68 ++++++--- drivers/pci/controller/pcie-mediatek.c | 25 ++- 9 files changed, 258 insertions(+), 140 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml