From patchwork Thu Oct 29 08:15:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuanjia Liu X-Patchwork-Id: 11865659 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9F87D92C for ; Thu, 29 Oct 2020 08:20:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 74AD920EDD for ; Thu, 29 Oct 2020 08:20:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="toC2fsuu" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727959AbgJ2IUh (ORCPT ); Thu, 29 Oct 2020 04:20:37 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:37205 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726392AbgJ2IUh (ORCPT ); Thu, 29 Oct 2020 04:20:37 -0400 X-UUID: 002690c0a75444e7a1a8e4e8a1957422-20201029 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=o3Qv9OfYUwrK9tVE0LcM9g+mhJJ29QPAQxRIwyUon6o=; b=toC2fsuuN27LunQYhD4azaeoj1sETWqhOJAtJg6AnEebdikM9i7hcB3Gkro4MYqnUlFUVC45mnLV5/BjWsVxGR/XHVgtRueF5kjmZQcPZui5ddzi2ePAan1v+8uHXWUxqWZwUvkoXVCl6Gl8GA9Hj5+Nx0cmN+jHjLJHmLym4KI=; X-UUID: 002690c0a75444e7a1a8e4e8a1957422-20201029 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 972438657; Thu, 29 Oct 2020 16:15:23 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Oct 2020 16:15:19 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 29 Oct 2020 16:15:19 +0800 From: Chuanjia Liu To: Rob Herring , Lorenzo Pieralisi CC: Bjorn Helgaas , Matthias Brugger , , , , , , Frank Wunderlich , Ryder Lee , Subject: [PATCH v7 0/4] PCI: mediatek: Spilt PCIe node to comply with hardware design Date: Thu, 29 Oct 2020 16:15:09 +0800 Message-ID: <20201029081513.10562-1-chuanjia.liu@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In current architecture, MSI domain will be inherited from the root bridge, and all of the devices will share the same MSI domain. Hence that, the PCIe devices will not work properly if the irq number which required is more than 32. Split the PCIe node for MT2712 and MT7622 platform to fix MSI issue and comply with the hardware design. change note: v7:dt-bindings file was modified as suggested by Rob, other file no change. v6:Fix yaml error. make sure driver compatible with old and new DTS format. v5:rebase for 5.9-rc1, no code change. v4:change commit message due to bayes statistical bogofilter considers this series patch SPAM. v3:rebase for 5.8-rc1. Only collect ack of Ryder, No code change. v2:change the allocation of MT2712 PCIe MMIO space due to the allocation size is not right in v1. Chuanjia Liu (4): dt-bindings: pci: mediatek: Modified the Device tree bindings PCI: mediatek: Add new method to get shared pcie-cfg base and irq arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622 ARM: dts: mediatek: Modified MT7629 PCIe node .../bindings/pci/mediatek-pcie-cfg.yaml | 39 +++++ .../devicetree/bindings/pci/mediatek-pcie.txt | 129 +++++++++++------- arch/arm/boot/dts/mt7629-rfb.dts | 3 +- arch/arm/boot/dts/mt7629.dtsi | 22 +-- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 75 ++++++---- .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 16 +- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 6 +- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 66 ++++++--- drivers/pci/controller/pcie-mediatek.c | 23 ++- 9 files changed, 248 insertions(+), 131 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml -- 2.18.0