From patchwork Tue Apr 20 06:17:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Smlhbmp1biBXYW5nICjnjovlu7rlhpsp?= X-Patchwork-Id: 12213369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61822C43460 for ; Tue, 20 Apr 2021 06:17:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2BCF7608FE for ; Tue, 20 Apr 2021 06:17:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229953AbhDTGSQ (ORCPT ); Tue, 20 Apr 2021 02:18:16 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:56414 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229577AbhDTGSQ (ORCPT ); Tue, 20 Apr 2021 02:18:16 -0400 X-UUID: e64997969f214ffe9c8521d07650a47c-20210420 X-UUID: e64997969f214ffe9c8521d07650a47c-20210420 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1752252126; Tue, 20 Apr 2021 14:17:40 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Apr 2021 14:17:39 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 20 Apr 2021 14:17:38 +0800 From: Jianjun Wang To: Bjorn Helgaas , Rob Herring , Marc Zyngier , Lorenzo Pieralisi , Ryder Lee CC: Philipp Zabel , Matthias Brugger , , , , , , Jianjun Wang , , , , , , , , Krzysztof Wilczyski , =?utf-8?q?Pali_Roh=C3=A1r?= Subject: [PATCH v10 0/7] PCI: mediatek: Add new generation controller support Date: Tue, 20 Apr 2021 14:17:16 +0800 Message-ID: <20210420061723.989-1-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: mtk15901 These series patches add pcie-mediatek-gen3.c and dt-bindings file to support new generation PCIe controller. Changes in v10: 1. Fix the subject line format in commit message; 2. Use EXPORT_SYMBOL_GPL() to export pci_pio_to_address(). Changes in v9: 1. Use mtk_pcie_parse_port() to get the hw resources; 2. Remove unnecessary logs; 3. Add local IRQ enable status save/restore instead of the enable/disable callbacks; 4. Fix typos. Changes in v8: 1. Add irq_clock to protect IRQ register access; 2. Mask all INTx interrupt when startup port; 3. Remove activate/deactivate callbacks from bottom_domain_ops; 4. Add unmask/mask callbacks in mtk_msi_bottom_irq_chip; 5. Add property information for reg-names. Changes in v7: 1. Split the driver patch to core PCIe, INTx, MSI and PM patches; 2. Reshape MSI init and handle flow, use msi_bottom_domain to cover all sets; 3. Replace readl/writel with their relaxed version; 4. Add MSI description in binding document; 5. Add pl_250m clock in binding document. Changes in v6: 1. Export pci_pio_to_address() to support compiling as kernel module; 2. Replace usleep_range(100 * 1000, 120 * 1000) with msleep(100); 3. Replace dev_notice with dev_err; 4. Fix MSI get hwirq flow; 5. Fix warning for possible recursive locking in mtk_pcie_set_affinity. Changes in v5: 1. Remove unused macros 2. Modify the config read/write callbacks, set the config byte field in TLP header and use pci_generic_config_read32/write32 to access the config space 3. Fix the settings of translation window, both MEM and IO regions works properly 4. Fix typos Changes in v4: 1. Fix PCIe power up/down flow 2. Use "mac" and "phy" for reset names 3. Add clock names 4. Fix the variables type Changes in v3: 1. Remove standard property in binding document 2. Return error number when get_optional* API throws an error 3. Use the bulk clk APIs Changes in v2: 1. Fix the typo of dt-bindings patch 2. Remove the unnecessary properties in binding document 3. dispos the irq mappings of msi top domain when irq teardown Jianjun Wang (7): dt-bindings: PCI: mediatek-gen3: Add YAML schema PCI: Export pci_pio_to_address() for module use PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192 PCI: mediatek-gen3: Add INTx support PCI: mediatek-gen3: Add MSI support PCI: mediatek-gen3: Add system PM support MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer .../bindings/pci/mediatek-pcie-gen3.yaml | 181 +++ MAINTAINERS | 1 + drivers/pci/controller/Kconfig | 13 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-mediatek-gen3.c | 1025 +++++++++++++++++ drivers/pci/pci.c | 1 + 6 files changed, 1222 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c