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Tue, 18 May 2021 17:38:12 +0000 (GMT) From: Shradha Todi To: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com, robh@kernel.org, bhelgaas@google.com, pankaj.dubey@samsung.com, p.rajanbabu@samsung.com, hari.tv@samsung.com, niyas.ahmed@samsung.com, l.mehra@samsung.com, Shradha Todi Subject: [PATCH 0/3] Add support for RAS DES feature in PCIe DW controller Date: Tue, 18 May 2021 23:16:15 +0530 Message-Id: <20210518174618.42089-1-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrLIsWRmVeSWpSXmKPExsWy7bCmuu6Z7iUJBocvslssacqw2HW3g93i 47SVTBYrvsxkt7jz/AajxeVdc9gszs47zmbx5vcLdosnUx6xWhzdGGyxaOsXdov/e3awW/Qe rnXg9Vgzbw2jx85Zd9k9Fmwq9di0qpPNo2/LKkaPLfs/M3p83iQXwB7FZZOSmpNZllqkb5fA lbHwxAnWghb+ij9nD7E3MC7i6WLk5JAQMJHobl/I1MXIxSEksJtR4taWA4wQzidGidnf10Fl PjNKXFq1nQ2m5ciZrywQiV2MEh1d+1khnBYmiWutz1hBqtgEtCQav3Yxg9giAtYSDa9WgRUx C8xhkvh/bBELSEJYwEti/ukGsLEsAqoSzw49BLN5Bawk7h39CLVOXmL1hgPMIM0SAo/YJe6v 2s4IkXCRWH54P1SRsMSr41vYIWwpiZf9bVB2vsTUC0+BlnEA2RUSy3vqIML2EgeuzAELMwto SqzfpQ8RlpWYegrkZU6gMJ9E7+8nTBBxXokd82BsZYkvf/ewQNiSEvOOXWaFsD0kFp7cBHaZ kECsxITv89gnMMrOQtiwgJFxFaNkakFxbnpqsWmBcV5quV5xYm5xaV66XnJ+7iZGcArR8t7B +OjBB71DjEwcjIcYJTiYlUR4t3svThDiTUmsrEotyo8vKs1JLT7EKM3BoiTOu+Lh5AQhgfTE ktTs1NSC1CKYLBMHp1QD0+vt60on3RPRyvTpKbmZ/6R+xs/ApLBWV5/XvN43o+wbosIk+c/+ sLnhLrTM4iH/BPZ7b0+4VLM2G1zJv99z/Y7dwUlh3Z8PsnfeLxXJcYqeaXtZ4NblmX+2qydq Kn9YtCLg3OklN/8skw6LdvZtj9/+2O/ixSCRGCfxx79z/oTJKD0/EDzryd/oti2mvmvOb/Rg mBETn5f64eymx9PSPySvunHlMYvy56p1URO5Kw5ujXq7a8LcGotfjy9KlnxuCP5y9ZSGzNfc lC87dkre8K/olL2vJVe4RtFvmqjZ0dO5G6bdTOELSz/Evtsw8r386QDF/x+jzO5sd28/eVL1 8HP763W6kgW5vyObOnqU+JRYijMSDbWYi4oTAZjlZzuQAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrCLMWRmVeSWpSXmKPExsWy7bCSnG7b78UJBtM3c1osacqw2HW3g93i 47SVTBYrvsxkt7jz/AajxeVdc9gszs47zmbx5vcLdosnUx6xWhzdGGyxaOsXdov/e3awW/Qe rnXg9Vgzbw2jx85Zd9k9Fmwq9di0qpPNo2/LKkaPLfs/M3p83iQXwB7FZZOSmpNZllqkb5fA lbHwxAnWghb+ij9nD7E3MC7i6WLk5JAQMJE4cuYrSxcjF4eQwA5GiSObL7JBJCQlPl9cxwRh C0us/PecHaKoiUmieeVUsCI2AS2Jxq9dzCC2iICtRMPfDmaQImaBFUwSbWcms4AkhAW8JOaf bgBrYBFQlXh26CGYzStgJXHv6EeobfISqzccYJ7AyLOAkWEVo2RqQXFuem6xYYFRXmq5XnFi bnFpXrpecn7uJkZwQGpp7WDcs+qD3iFGJg7GQ4wSHMxKIrzbvRcnCPGmJFZWpRblxxeV5qQW H2KU5mBREue90HUyXkggPbEkNTs1tSC1CCbLxMEp1cC0WXSzJF+Xrb/7XskdGv7mfBHLq7d6 6cWdbm//Xvwk8dG259ZcsVIhV/1j+eqmv9duM517ICz8+aee91pW7/4ZC8yVZ5eNOxvKeUpc peFl8PsNek8tJyl8e/zCubf6skNulw/X7YUzJEU3LZp4hfVUhLDmXaOyUA+dZ5sS3tsUrCxX E7l5rfdKVcYZtfqXvme+LdKe85rN++6CDf8Vdf199yZ/eup2IHbZka6QOcqnvf8c6Oxn2bBE iud0s5D9/LS2e1F7m1eLrOfsOiG5qGqluUvEioNWJie6FrhevuGmvyI36sTHR4vP1AYKHzG4 KGuofe74sQ+vCqI5mROrLrvLdgoJ/m26rKBRsCRBrkCJpTgj0VCLuag4EQApp2ATtwIAAA== X-CMS-MailID: 20210518173814epcas5p46b312c35e11c130a6a8d043f10d12ee4 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20210518173814epcas5p46b312c35e11c130a6a8d043f10d12ee4 References: Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org DesignWare controller provides a vendor specific extended capability called RASDES as an IP feature. This extended capability provides hardware information like: - Debug registers to know the state of the link or controller. - Error injection mechanisms to inject various PCIe errors including sequence number, CRC - Statistical counters to know how many times a particular event occurred However, in Linux we do not have any generic or custom support to be able to use this feature in an efficient manner. This is the reason we are proposing this framework. Debug and bring up time of high-speed IPs are highly dependent on costlier hardware analyzers and this solution will in some ways help to reduce the HW analyzer usage. The debugfs entries can be used to get information about underlying hardware and can be shared with user space. Separate debugfs entries has been created to cater to all the DES hooks provided by the controller. The debugfs entries interacts with the RASDES registers in the required sequence and provides the meaningful data to the user. This eases the effort to understand and use the register information for debugging. Shradha Todi (3): PCI: dwc: Add support for vendor specific capability search PCI: debugfs: Add support for RAS framework in DWC PCI: dwc: Create debugfs files in DWC driver drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 1 + .../controller/dwc/pcie-designware-debugfs.c | 544 ++++++++++++++++++ .../controller/dwc/pcie-designware-debugfs.h | 133 +++++ drivers/pci/controller/dwc/pcie-designware.c | 21 + drivers/pci/controller/dwc/pcie-designware.h | 5 + 6 files changed, 713 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-designware-debugfs.c create mode 100644 drivers/pci/controller/dwc/pcie-designware-debugfs.h