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Tue, 21 Jun 2022 04:36:58 -0700 Envelope-to: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh@kernel.org Received: from [10.140.9.24] (port=39508 helo=xhdarjunv40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o3cBl-000Bco-Hu; Tue, 21 Jun 2022 04:36:57 -0700 From: Bharat Kumar Gogada To: , , CC: , , , , Bharat Kumar Gogada Subject: [PATCH v5 0/2] Add support for Xilinx Versal CPM5 Root Port Date: Tue, 21 Jun 2022 17:06:51 +0530 Message-ID: <20220621113653.2354462-1-bharat.kumar.gogada@xilinx.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 643bc552-cb0d-47e9-d71f-08da537a5a97 X-MS-TrafficTypeDiagnostic: MN2PR02MB6432:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2022 11:36:59.6425 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 643bc552-cb0d-47e9-d71f-08da537a5a97 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT035.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB6432 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Xilinx Versal CPM5 has few changes with existing CPM block. - CPM5 has dedicated register space for control and status registers. - CPM5 legacy interrupt handling needs additonal register bit to enable and handle legacy interrupts. Changes in v5: - Added of_device_get_match_data to identify CPM version. Bharat Kumar Gogada (2): dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port PCI: xilinx-cpm: Add support for Versal CPM5 Root Port .../bindings/pci/xilinx-versal-cpm.yaml | 48 ++++++++++++-- drivers/pci/controller/pcie-xilinx-cpm.c | 62 ++++++++++++++++++- 2 files changed, 103 insertions(+), 7 deletions(-)