From patchwork Wed Oct 26 01:58:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Ranostay X-Patchwork-Id: 13020038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CC33C38A02 for ; Wed, 26 Oct 2022 01:59:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231681AbiJZB7N (ORCPT ); Tue, 25 Oct 2022 21:59:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230090AbiJZB7M (ORCPT ); Tue, 25 Oct 2022 21:59:12 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFD68D0CC1 for ; Tue, 25 Oct 2022 18:59:10 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29Q1x0E4064381; Tue, 25 Oct 2022 20:59:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666749540; bh=WiOkBDKr/bcAJ5rhRo5Kk+r8jvcdJW1mDkoDLgO62LI=; h=From:To:CC:Subject:Date; b=msMgA/VpMkJeacGq1iY4Z1h2nAIJLhvt4DlQYIualw9ZTZJBkm6FpkPNoQhubuYe3 22eNf8EibwxVRHaJIgrWsZ70IAlW/gOv8UW3loGOQTcJxBA0+vUJ3escHVW7aPpGYA vNykTatLJQoPjnYS1I7mCbfP0xALXYSEnXxwuBpQ= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29Q1x0vm017469 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 25 Oct 2022 20:59:00 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 25 Oct 2022 20:59:00 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 25 Oct 2022 20:59:00 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29Q1wtPu016572; Tue, 25 Oct 2022 20:58:57 -0500 From: Matt Ranostay To: , , , , CC: , , Matt Ranostay Subject: [PATCH v4 0/3] PCI: add 4x lane support for pci-j721e controllers Date: Tue, 25 Oct 2022 18:58:47 -0700 Message-ID: <20221026015850.591044-1-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Adding of dditional support to Cadence PCIe controller (i.e. pci-j721e.c) for up to 4x lanes, and reworking of driver to define maximum lanes per board configuration. Changes from v1: * Reworked 'PCI: j721e: Add PCIe 4x lane selection support' to not cause regressions on 1-2x lane platforms Changes from v2: * Correct dev_warn format string from %d to %u since lane count is a unsigned integer * Update CC list Changes from v3: * Use the max_lanes setting per chip for the mask size required since bootloader could have set num_lanes to a higher value that the device tree which would leave in an undefined state * Reorder patches do the previous change to not break bisect * Remove line breaking for dev_warn to allow better grepping and since no strict 80 columns anymore Matt Ranostay (3): PCI: j721e: Add per platform maximum lane settings PCI: j721e: Add PCIe 4x lane selection support PCI: j721e: Add warnings on num-lanes misconfiguration drivers/pci/controller/cadence/pci-j721e.c | 28 ++++++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-)