From patchwork Thu Jul 27 10:39:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 13329939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2ACAC001E0 for ; Thu, 27 Jul 2023 10:40:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232697AbjG0KkL (ORCPT ); Thu, 27 Jul 2023 06:40:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232480AbjG0KkK (ORCPT ); Thu, 27 Jul 2023 06:40:10 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCD8726AB; Thu, 27 Jul 2023 03:40:08 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id CFC2680E2; Thu, 27 Jul 2023 18:39:58 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 27 Jul 2023 18:39:58 +0800 Received: from localhost.localdomain (113.72.147.196) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 27 Jul 2023 18:39:57 +0800 From: Minda Chen To: =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Daire McNamara , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Emil Renner Berthing CC: , , , Philipp Zabel , "Mason Huo" , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v2 0/4] Refactoring Microchip PCIe driver and add StarFive PCIe Date: Thu, 27 Jul 2023 18:39:45 +0800 Message-ID: <20230727103949.26149-1-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [113.72.147.196] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patchset final purpose is add PCIe driver for StarFive JH7110 SoC. JH7110 using PLDA XpressRICH PCIe IP. Microchip PolarFire Using the same IP and have commit their codes, which are mixed with PLDA controller codes and Microchip platform codes. For re-use the PLDA controller codes, I request refactoring microchip codes, move PLDA common codes to PLDA files. Desigware and Cadence is good example for refactoring codes. So first step is extract the PLDA common codes from microchip, and refactoring the microchip codes.(patch1 - 2) Then, add Starfive codes. (patch3 - 4) This patchset is base on v6.5-rc1 patch1 is move PLDA XpressRICH PCIe host common properties dt-binding docs from microchip,pcie-host.yaml patch2 is extracting the PLDA common codes from microchip Polarfire PCIe codes. The change list in the commit message. patch3 is add StarFive JH7110 PCIe dt-binding doc. patch4 is add StarFive JH7110 Soc PCIe codes. I have noticed that Daire have changed microchip's codes. https://patchwork.kernel.org/project/linux-pci/cover/20230630154859.2049521-1-daire.mcnamara@microchip.com/ I have changed patch2 base on their commits. StarFive PCIe driver still can work. But their codes is under reviewed and maybe changing. Do not base on their changes first. I will base on their commit to change patch2 as soon as their commits are accepted. previous version: v1:https://patchwork.kernel.org/project/linux-pci/cover/20230719102057.22329-1-minda.chen@starfivetech.com/ change: v2: patch1: - squash dt-bindings patches to patch1 - add 'required' list. - plda doc rename to plda,xpressrich-axi-common.yaml patch2: - squash the microchip modification patch to patch 2. patch3: - remove the plda common required property. patch4: - Sync the hide rc bar ops with config read function. - Revert the T_PVPERL to 100ms and add comments for the source. - Replace the link check function by the standard link ops. - Convert to new pm ops marcos. - Some formats modification. - pcie-plda-host modification merge to patch4. other: - remove the pcie-plda-plat.c - remove the starfive dts patch first. for it depends on stg clock and syscon setting. Minda Chen (4): dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties PCI: plda: Get common codes from Microchip PolarFire host dt-bindings: PCI: Add StarFive JH7110 PCIe controller PCI: starfive: Add JH7110 PCIe controller .../bindings/pci/microchip,pcie-host.yaml | 49 +- .../pci/plda,xpressrich3-axi-common.yaml | 69 ++ .../bindings/pci/starfive,jh7110-pcie.yaml | 133 ++++ MAINTAINERS | 19 +- drivers/pci/controller/Kconfig | 9 +- drivers/pci/controller/Makefile | 2 +- drivers/pci/controller/plda/Kconfig | 31 + drivers/pci/controller/plda/Makefile | 4 + .../{ => plda}/pcie-microchip-host.c | 594 ++-------------- drivers/pci/controller/plda/pcie-plda-host.c | 665 ++++++++++++++++++ drivers/pci/controller/plda/pcie-plda.h | 242 +++++++ drivers/pci/controller/plda/pcie-starfive.c | 438 ++++++++++++ 12 files changed, 1645 insertions(+), 610 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml create mode 100644 drivers/pci/controller/plda/Kconfig create mode 100644 drivers/pci/controller/plda/Makefile rename drivers/pci/controller/{ => plda}/pcie-microchip-host.c (50%) create mode 100644 drivers/pci/controller/plda/pcie-plda-host.c create mode 100644 drivers/pci/controller/plda/pcie-plda.h create mode 100644 drivers/pci/controller/plda/pcie-starfive.c base-commit: 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5