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Tue, 30 Jul 2024 06:42:39 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , John Stultz , Thomas Gleixner , "Anna-Maria Behnsen" , Frederic Weisbecker , , Bjorn Helgaas , , Ingo Molnar , Borislav Petkov , Dave Hansen , , Carolina Jubran , Bar Shapira , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net-next V3 0/3] mlx5 PTM cross timestamping support Date: Tue, 30 Jul 2024 16:40:51 +0300 Message-ID: <20240730134055.1835261-1-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3A:EE_|BY5PR12MB4244:EE_ X-MS-Office365-Filtering-Correlation-Id: e44a10a5-291e-42f4-10e5-08dcb09d8589 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: YYCnM+RM+pIr8pYtmb5r4N8ufd6IZ/T/Yvc45b4VORvicIMYePcb2cpodKWUTA5rlzyHhz4dZu9jxpzd1DTft3hzIJG8bFIFs5Kd/iiQmmzXg0UuLcWQqP9y3bUb/7rbgwjRGx20NojnWRpSM9fNAcGQQ+V7uMisjx5+l8eMIOmqaUfO60t2+gvtsYvguqt6AsbJGQ+V3dciKS604aTD7Q/cQVY9PbHVXkG8u+XO9UFwzb8UmIiA0xJUberdgMiSsuuBUqITO6wiwZ0Vw34e6qR3w4muTA8AgjXH2ovYb4w4LlgFZ26ub0NYNI3mhsmvJI1MV+Sx788a66+ovhkz5z9RaSMEz0apcNEcEgzIe+XKGRi0Oog72oZjRIOKoz6PjwMOBY8ZHRltFjKX2uniEz22UHxTSRxwR6MI3c8G0KvxrPud8fFDHVSxm41XN7eDUR4po55gpwLTz7ukVrthhigG/Sxykankr0NRem28CFlLB0zfhFM71jdA4G0SROYJ/w/GNrZHqtXjr1FuHwDbvHATOa2MrSBkPeQn/+eyCYNYXV3yX4boBUIL274vApyMI51d8zMgDyI5ENCPwuxHXKFB3v2PWh6KVrjm2T3Cl1AlUTbRtny8muMk4l4pbt4YXjHC8VvofD84KnTV8i8+jOro24hsw0BVuJGXTDj4H2xYc6+gwsBzM1fI6mX1k6YWaHSP/I9nW/vaseFKZMNEYJwWvqL+3zUHQVKajADDIRitFxFlO0ZAIZ4uzaybQMf6apjmDoUchtFTtBHNHwfd4cQJFviKV/NPJ20+wHSaXDigd4wuU0fb24oLXMQoYVXFSr0k/Z8tMiCeTfDml0GrSuToBq3OlDC3k+DbL5IUuLNXLfeNVFGyzv0cEj7KbKZwo3JkxO29t8omgAI3jVhClHnMFQHqPy/yDpizvyVyJnJ1cvUhpV5HwfFs5qk04/2rwMJOk2/AiVGBFzk4X5+whhay0s31AG9iS+kZlTEWMylfkVcKOIzgrhrT+D2D/zi2Wc9vBNrpt22iBiShn+7aGQLwxtgOe73L+qV8SMGJrvHgJaf9seOUzwplOmt2PAbhcikXrfrXA/6YpCnkZqe8Vcbi2x4Zgiypoyhe/FHL1jMhfly+AjnQNIcjMM4bcDhpa8EhFDmzMkJnNYm8niY6jK/QNOnqO/wtiaq3BRU/z/GQyPmk+XXJdUX/wEYBECLxM4hr4x4OHOxpM2q1pcwzP7hDAj9JA3kS8ZZmCdwmZaxSfkw5PJXnJ+KaR91HLQ5M0Qo8y+kvcBheXXHHK0ywOBK4msId3DnrUq+YavYOTpkd6kmLIfcaN+6sRD/u4vrE7JDCpq0MwmSYKJv31t1gCuObDvbywYxYE0NcbJRP4kYQFPdOk9wPZiDI4XD0gApE6rY7zmklLuDJsydKL7rsAd9H3/Dex+BtcwFbqqoeZmkrNQbM8/SLYI/4/eHHOfxA X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 13:42:57.5380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e44a10a5-291e-42f4-10e5-08dcb09d8589 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4244 Hi, This is V3. You can find V2 as part of a larger series here: https://lore.kernel.org/netdev/d1dba3e1-2ecc-4fdf-a23b-7696c4bccf45@gmail.com/T/ This patchset by Rahul and Carolina adds PTM (Precision Time Measurement) support to the mlx5 driver. PTM is a PCI extended capability introduced by PCI-SIG for providing an accurate read of the device clock offset without being impacted by asymmetric bus transfer rates. The performance of PTM on ConnectX-7 was evaluated using both real-time (RTC) and free-running (FRC) clocks under traffic and no traffic conditions. Tests with phc2sys measured the maximum offset values at a 50Hz rate, with and without PTM. Results: 1. No traffic +-----+--------+--------+ | | No-PTM | PTM | +-----+--------+--------+ | FRC | 125 ns | <29 ns | +-----+--------+--------+ | RTC | 248 ns | <34 ns | +-----+--------+--------+ 2. With traffic +-----+--------+--------+ | | No-PTM | PTM | +-----+--------+--------+ | FRC | 254 ns | <40 ns | +-----+--------+--------+ | RTC | 255 ns | <45 ns | +-----+--------+--------+ Series generated against: commit 1722389b0d86 ("Merge tag 'net-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net") Thanks, Tariq. V3: - Rebased on latest. As a result, had to replace the call to the recently removed function convert_art_ns_to_tsc(). - Added more CCs to the series per Jakub's feedback. - Added perf numbers. Carolina Jubran (1): net/mlx5: Add support for enabling PTM PCI capability Rahul Rameshbabu (2): net/mlx5: Add support for MTPTM and MTCTR registers net/mlx5: Implement PTM cross timestamping support drivers/net/ethernet/mellanox/mlx5/core/fw.c | 1 + .../ethernet/mellanox/mlx5/core/lib/clock.c | 91 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/main.c | 6 ++ include/linux/mlx5/device.h | 7 +- include/linux/mlx5/driver.h | 2 + include/linux/mlx5/mlx5_ifc.h | 43 +++++++++ 6 files changed, 149 insertions(+), 1 deletion(-) Tested-by: Vadim Fedorenko