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Many PCI controllers are dual-role controllers, supporting both Root Complex (RC) and Endpoint (EP) modes. The EP side also needs similar information for proper address translation. This commit introduces several changes to add 'ranges' support for PCI endpoint devices: 1. **Modify of_address.c**: Add support for the new `device_type` "pci-ep", enabling it to parse 'ranges' using the same functions as for PCI devices. 2. **Update DesignWare PCIe EP driver**: Enhance the driver to support 'ranges' when 'addr_space' is missing, maintaining compatibility with existing drivers. 3. **Update binding documentation**: Modify the device tree bindings to include 'ranges' support and make 'addr_space' an optional entry in 'reg-names'. 4. **Add i.MX8QXP EP support**: Incorporate support for the i.MX8QXP PCIe EP in the driver. i.MX8QXP PCIe dts is upstreaming. Below is pcie-ep part. pcieb_ep: pcie-ep@5f010000 { compatible = "fsl,imx8q-pcie-ep"; reg = <0x5f010000 0x00010000>; reg-names = "dbi"; #address-cells = <3>; #size-cells = <2>; device_type = "pci-ep"; ranges = <0x82000000 0 0x80000000 0x70000000 0 0x10000000>; num-lanes = <1>; interrupts = ; interrupt-names = "dma"; clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, <&pcieb_lpcg IMX_LPCG_CLK_4>, <&pcieb_lpcg IMX_LPCG_CLK_5>; clock-names = "dbi", "mstr", "slv"; power-domains = <&pd IMX_SC_R_PCIE_B>; fsl,max-link-speed = <3>; num-ib-windows = <6>; num-ob-windows = <6>; status = "disabled"; }; These changes improve PCIe EP support by allowing proper address translation using 'ranges', ensuring compatibility with devices that rely on this information. Signed-off-by: Frank Li --- Frank Li (9): dt-bindings: PCI: pci-ep: Document 'ranges' property of: address: Add argument 'name' for of_node_is_pcie() of: address: Add device type pci-ep dt-bindings: PCI: snps,dw-pcie-ep: 'addr_space' not required if 'ranges' present PCI: dwc: ep: Replace phys_base and addr_size with range PCI: dwc: ep: Use 'ranges' from DT if 'addr_space' is missing dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext() PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support .../devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 42 +++++++++++++++++++++- Documentation/devicetree/bindings/pci/pci-ep.yaml | 30 ++++++++++++++++ .../bindings/pci/snps,dw-pcie-common.yaml | 4 +-- .../devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 21 ++++++++--- drivers/of/address.c | 30 ++++++++++++---- drivers/pci/controller/dwc/pci-imx6.c | 24 ++++++++++++- drivers/pci/controller/dwc/pcie-artpec6.c | 2 +- drivers/pci/controller/dwc/pcie-designware-ep.c | 23 ++++++++---- drivers/pci/controller/dwc/pcie-designware.h | 4 +-- 9 files changed, 157 insertions(+), 23 deletions(-) --- base-commit: 909eac36208b70a22fd0d1c3097e3af98dca7599 change-id: 20240918-pcie_ep_range-4c5c5e300e19 Best regards, --- Frank Li